JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV Year VLSI DESIGN Previous Question Paper (September - 2021 - R16)

A CMOS inverter consists of a PMOS transistor connected in series with an NMOS transistor. The source of the PMOS is connected to the supply voltage (V_DD), and the source of the NMOS is connected to ground (V_SS). The gates of both transistors are tied together to form the input (V_in), and the drains are tied together to form the output (V_out).

The DC transfer characteristics are divided into five distinct regions based on the operating states of the transistors:

1. Region 1 (V_in < V_TN): The NMOS is in cutoff, and the PMOS is in linear region. V_out = V_DD.
2. Region 2 (V_TN ≤ V_in < V_M): The NMOS is in saturation, and the PMOS is in linear region. V_out begins to drop.
3. Region 3 (V_in = V_M): Both transistors are in saturation. This is the switching threshold where V_in = V_out. The threshold voltage V_M is given by:
   V_M = (V_TN + sqrt(k_p/k_n)(V_DD - |V_TP|)) / (1 + sqrt(k_p/k_n))
4. Region 4 (V_M < V_in ≤ V_DD - |V_TP|): The NMOS is in linear region, and the PMOS is in saturation.
5. Region 5 (V_in > V_DD - |V_TP|): The PMOS is in cutoff, and the NMOS is in linear region. V_out = 0.

The current equation for both transistors in saturation is:

where k = μC_ox(W/L). The transition is characterized by high gain at the switching threshold, making the CMOS inverter an ideal building block for digital logic circuits due to its high noise margin and low static power dissipation.