Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech III VLSI DESIGN Previous Question Paper (February/March - 2022 - R18)

B.Tech | III | III-II | R18 | February/March - 2022

Answer PaperPaper Code: 156DFMaximum Marks: 75Time: 3 hours

Answer any five questions. All questions carry equal marks.

Main

1
Explain the following:
15 marks
a
Transconductance gm
5 marks

Answer

Transconductance (gm) is a measure of the sensitivity of the drain current (ID) to changes in the gate-source voltage (VGS) while the drain-source voltage (VDS) remains constant. It represents the gain of the MOSFET as a voltage-controlled current source.

gm = ∂ID / ∂VGS

In the saturation region, it is expressed as gm = √(2μnCox(W/L)ID). A higher transconductance indicates that a small change in input voltage results in a large change in output current, which is critical for high-gain amplifier design.

b
Figure of merit wo
5 marks

Answer

The figure of merit (ωo), often referred to as the unity-gain bandwidth or transition frequency (fT), represents the frequency at which the short-circuit current gain of a transistor drops to unity.

ωT = gm / (Cgs + Cgd)

This parameter serves as a benchmark for the speed of a MOSFET. It indicates the upper frequency limit for the device's operation as an amplifier. A higher ωT implies that the transistor can respond faster to high-frequency signals, making it a vital metric for high-speed digital and analog circuit performance.

c
Pass transistor.
5 marks

Answer

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215 marks
a
Derive the expression for the threshold voltage of MOSFET.
8 marks

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b
Derive the expression for transfer characteristics of CMOS Inverter.
7 marks

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315 marks
a
Explain steps in VLSI Design flow.
8 marks

Answer

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b
Design a Stick Diagram for 2-input nMOS NAND gate.
7 marks

Answer

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415 marks
a
Explain 2µm CMOS design rules for wires.
7 marks

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b
Draw the Layout Diagrams for NOR and XOR Gate.
8 marks

Answer

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515 marks
a
Explain the model for deviation of time delay.
7 marks

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b
Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit.
8 marks

Answer

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6
Define the following and explain the significance of each term in VLSI circuits:
15 marks
a
Fan in and Fan out
7 marks

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b
Choice of layers.
8 marks

Answer

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715 marks
a
Design a 4-bit Parity generator and draw its logic diagram.
8 marks

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b
Explain the operation of SRAM cell with its construction.
7 marks

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815 marks
a
What is CPLD? Draw its basic structure and give its applications.
8 marks

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b
Explain about system level test techniques in detail.
7 marks

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This page contains the question paper of VLSI DESIGN from Jawaharlal Nehru Technological University Hyderabad for B.Tech ETM III III-II, February/March - 2022, R18.

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