Jawaharlal Nehru Technological University Hyderabad
Jawaharlal Nehru Technological University Hyderabad B.Tech III VLSI DESIGN Previous Question Paper (May - 2019 - R15)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
PART - A
List the basic process for IC fabrication.
Answer
The basic IC fabrication process involves silicon wafer preparation, epitaxial growth, oxidation, photolithography, etching, diffusion or ion implantation, and metallization.
Compare CMOS and BiCMOS logic.
Answer
CMOS logic offers high packing density and low static power dissipation, making it ideal for VLSI circuits. BiCMOS combines the high input impedance and low power of CMOS with the high speed and high drive current capability of bipolar transistors, though it is more complex and expensive to manufacture.
What are the different MOS layers?
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Give the various color coding used in stick diagram.
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How do understand about MOS transistor as a switch?
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What is meant parasitic capacitance?
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What is meant by bit-sliced datapath organization?
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Determine propagation delay of n-bit carry select adder.
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What is the need of testing?
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What are the types of programmable devices?
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PART - B
Explain the operation of PMOS Enhancement transistor.
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Explain with neat diagrams the various CMOS fabrication technology.
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Derive Id-Vds relationship of MOS in all cases.
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Draw the VLSI design flow diagram and explain.
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Draw the circuit diagram stick diagram and layout of 2-input CMOS NAND gate.
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Explain the concept of Delay estimation, logical effort and sizing of MOSFET.
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Design a 2-input AND gate using switch logic.
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Describe pass transistor briefly with example.
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Implement EX-OR logic gate using CMOS logic.
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Explain the operation of 4 bit parallel Adder / subtractor.
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Draw the structure of a dynamic RAM and explain it’s operation.
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What are the types of ROMs? Write a block diagram of a ROM and explain it’s operation.
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Design a 16:1 multiplexer using 4:1 multiplexers.
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Realize the following function using PAL F1(x, y, z) = ∑ (1, 2, 4, 5, 7) and F2(x, y, z) = ∑ (0, 1, 3, 5, 7)
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Explain system-level test techniques.
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With neat sketch explain the CLB, IOB and programmable interconnects of an FPGA device.
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Explain self-test technique testing.
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