JNTUH B.Tech II DIGITAL LOGIC DESIGN AND COMPUTER ORGANIZATION Previous Question Paper (March - 2022 - R15)

A computer is a complex system composed of several interconnected functional units, each performing a specific task. The basic functional units are:

1. Central Processing Unit (CPU): The brain of the computer. It performs all the processing and control operations. It consists of:
   • Arithmetic Logic Unit (ALU): Performs arithmetic (addition, subtraction, etc.) and logic (AND, OR, NOT, etc.) operations on data.
   • Control Unit (CU): Directs the operation of the processor. It fetches instructions from memory, decodes them, and generates control signals to execute them. It controls the flow of data between other units.
   • Registers: Small, high-speed storage locations within the CPU used to hold data, instructions, and addresses temporarily during processing.
2. Memory Unit: Stores data and instructions. It can be broadly classified into:
   • Primary Memory (Main Memory): Fast memory (like RAM) that holds data and instructions currently being used by the CPU. It is volatile.
   • Secondary Memory (Auxiliary Memory): Slower, non-volatile storage (like hard drives, SSDs) used for long-term storage of data and programs.
3. Input Unit: Allows data and instructions to be entered into the computer. Examples include keyboards, mice, scanners, and microphones.
4. Output Unit: Displays or presents the results of the computer's processing to the user. Examples include monitors, printers, and speakers.
5. Bus Structure: Connects the various functional units and allows them to communicate with each other. It consists of:
   • Data Bus: Carries data between units.
   • Address Bus: Carries memory addresses from the CPU to memory and I/O devices.
   • Control Bus: Carries control signals and timing information from the control unit to other units.

The single bus structure is a simplified model of a computer's internal organization where all the major components (CPU, memory, I/O devices) are connected via a single set of wires called a bus. This bus serves as the communication pathway for data, addresses, and control signals.

Components and Operation:

• CPU: Contains registers (e.g., Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Instruction Register (IR), Accumulator (AC)) and the ALU. It initiates data transfers and computations.
• Memory: Stores program instructions and data. It has an address bus interface to specify locations and a data bus interface for reading/writing data.
• I/O Devices: Input and output peripherals that interact with the system.
• Bus: A shared communication pathway consisting of:
  • Data Bus: A bidirectional bus that carries data between the CPU, memory, and I/O devices. The width of the data bus determines the amount of data that can be transferred per cycle (e.g., 8-bit, 16-bit, 32-bit).
  • Address Bus: A unidirectional bus that carries the memory address or I/O port number from the CPU to the memory or I/O device. The width of the address bus determines the maximum addressable memory space.
  • Control Bus: Carries control signals such as read/write signals, clock signals, interrupt requests, and bus request/grant signals. These signals manage the flow of information and coordinate the activities of the connected units.

Operation Example (Memory Read):

1. The CPU places the address of the desired memory location onto the address bus. This address is typically loaded into the MAR.
2. The CPU asserts the read control signal on the control bus.
3. The memory unit decodes the address and retrieves the data from the specified location.
4. The memory unit places the retrieved data onto the data bus.
5. The CPU reads the data from the data bus into one of its registers (e.g., MDR, then AC).

Advantages:

• Simplicity in design and implementation.
• Reduced wiring complexity compared to multiple buses.

Disadvantages:

• Performance bottleneck: Since all communication shares the same bus, only one transfer can occur at a time, limiting the overall speed of the computer.
• Potential for bus contention if multiple devices try to use the bus simultaneously.