Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech III SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (August - 2022 - R13)

B.Tech | III | I | R13 | August - 2022

Answer PaperPaper Code: 115BEMaximum Marks: 75Time: 3 hours

Answer any five questions. All questions carry equal marks.

Main

115 marks
a

Explain the two laws of De Morgan’s theorem.

6 marks

Answer

De Morgan's theorems are fundamental in Boolean algebra for simplifying logic expressions and converting between AND/OR logic. The two laws are:

  1. The complement of a product of variables is equal to the sum of the complements of the individual variables:
    (XY)' = X' + Y'
  2. The complement of a sum of variables is equal to the product of the complements of the individual variables:
    (X + Y)' = X'Y'

These theorems demonstrate that an AND gate with inverted inputs is equivalent to a NOR gate, and an OR gate with inverted inputs is equivalent to a NAND gate.

b

Expand

A(A+B)(A+B+C)
to max terms and min terms.

9 marks

Answer

Given the expression:

F = A(A+B)(A+B+C)

First, simplify the expression using Boolean algebraic laws:

F = A(A + B + 0)(A + B + C)
F = A(A + B + 0 ⋅ C) = A(A + B) = A

To expand into minterms and maxterms for three variables (A, B, C):

Minterms:

F = A(B + B')(C + C') = ABC + ABC' + AB'C + AB'C'

In summation notation:

F = Σm(4, 5, 6, 7)

Maxterms:

F = A + BB' + CC' = (A + B + C)(A + B + C')(A + B' + C)(A + B' + C')

In product notation:

F = ΠM(0, 1, 2, 3)

2

Simplify the following Boolean expressions to minimum number of literals:

15 marks
a

ABC + A'B + ABC'

5 marks

Answer

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b

(BC' + A'D)(AB' + CD')

5 marks

Answer

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c

x'yz + xz

5 marks

Answer

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3

Simplify the function using Karnaugh map method and realize using basic gates and using only anyone universal gate.

F (A, B, C, D) = ∑(4, 5, 7, 12, 14, 15) + ∑d (3, 8, 10)
15 marks

Answer

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4

Minimize the following function using tabular minimization and realize it with logic gate.

F (A, B, C, D, F) = ∑ m (0, 1, 2, 8, 9, 15, 17, 21, 24, 25, 27, 31)
15 marks

Answer

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515 marks
a

Draw the logic diagram of edge triggered JK flip flop using NAND gates and explain its truth table.

8 marks

Answer

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b

Design clocked T Flip-Flop and explain its working with neat waveforms and truth table.

7 marks

Answer

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615 marks
a

Discuss the timing and triggering considerations with respect to flip flops.

7 marks

Answer

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b

Explain the operation of a master-slave JK flip flop with the help of a diagram.

8 marks

Answer

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715 marks
a

Explain the operation of a Johnson counter with a neat diagram.

7 marks

Answer

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b

Draw the diagram of 4-bit parallel input serial output shift register and explain.

8 marks

Answer

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815 marks
a

What are the capabilities and limitations of finite state machines.

7 marks

Answer

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b

Explain the procedure of state minimization using the merger graph and merger table.

8 marks

Answer

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About this paper

This page contains the question paper of SWITCHING THEORY AND LOGIC DESIGN from Jawaharlal Nehru Technological University Hyderabad for B.Tech MECT-MCT-MEM III I, August - 2022, R13.

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