JNTU
JNTU B.Tech II SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (October - 2020 - R13)
Answer any five questions. All questions carry equal marks.
Main
For the given three variable Boolean expressions
Draw the logic circuit for original expression using Basic Logic gates
Answer
The expression f(a,b,c) = Σm(0,1,3,4,7) corresponds to the sum of minterms: f = a'b'c' + a'b'c + a'bc + ab'c' + abc. To implement this using basic logic gates, each minterm is generated using a 3-input AND gate (with inverters for complemented variables). These five AND gate outputs are then connected to a single 5-input OR gate.
Reduce the Boolean expression using Boolean algebra
Answer
Using Boolean algebra to simplify f = a'b'c' + a'b'c + a'bc + ab'c' + abc:
Since (c' + c) = 1:
Group terms:
Using the identity (x + x'y) = x + y and (x'y' + xy) = (x ⊕ y)':
Alternatively, grouping minterms (0,1) and (0,4) and (3,7) and (1,3):
Further simplification yields f = a'b' + a'c + bc + b'c'.
Draw the logic circuit for the reduced expression using basic logic gates
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What is your observation after solving (a) and (c).
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Simplify the following expressions and implement them with NAND gate circuits:
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Using K-map obtain the minimal SOP expression for the given switching function and implement it using basic logic gates:
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Design a full adder and implement it using 3 to 8 Decoder Circuit.
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Simplify the given expression using Quine-McCluskey method:
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Design and implement 2-bit comparator circuit using suitable gates.
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With a neat diagram explain operation of T flip-flop and derive its truth table, characteristic equation and excitation table.
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Convert a D flip-flop into JK flip-flop using standard procedure.
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With a neat diagram explain operation of D flip-flop and derive its truth table, characteristic equation and excitation table.
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Realize a SR flip-flop using D flip-flop using standard procedure.
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Design a Mod-5 synchronous counter using T flip-flops.
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Design a 3-bit bidirectional shift register using JK flip-flops having right and left data inputs and Mode control M such that M=0 left shift, M=1 right shift.
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Draw the ASM chart for binary multiplier and design the control circuit using JK flip-flop and gates.
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