JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B. Tech III SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (January/February - 2023 - R13)
Note: i) Question paper consists of Part A, Part B. ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions. iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.
Part A
What does the base or radix of a number system indicate?
Answer
The base or radix of a number system indicates the total number of unique digits or symbols available in that system to represent values. It also defines the weight associated with each digit position in a number, where each position represents a power of the radix.
What is a NAND gate why it is called as universal gate?
Answer
A NAND gate is a digital logic gate that produces a low output (0) only when all its inputs are high (1); otherwise, it produces a high output (1). It is effectively an AND gate followed by a NOT gate, represented by the Boolean expression Y = (A ⋅ B)'.
It is called a universal gate because any Boolean function or logic circuit can be implemented using only NAND gates. By connecting NAND gates in specific configurations, one can construct all other fundamental logic gates, including NOT, AND, OR, NOR, and XOR gates, without requiring any other type of logic element.
How do you convert a POS form in SOP form?
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What are don’t cares? How don’t care minterms and maxterms used in the tabular method?
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What is a Flip Flop? How many flip flops are required for storing n bits if information?
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Distinguish between asynchronous and synchronous latches.
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What is a state diagram give its advantages?
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What is the difference between synchronous counter and asynchronous counter?
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What is a finite state machine give its limitations?
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Give the features of ASM chart.
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Part B
Perform the following subtractions in EX-3 code (i) 267-175, (ii) 57.6-27.8
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Simplify the functions: i) f(A,B,C)=(A+B)(A+C′)+A′B′+A′C′, ii) f = A+B[AC+(B+C′)D].
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Draw the logic diagram using only two input NAND gates to implement the following expression F=(AB+A′B′)(CD+C′D).
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Give three possible ways to express the function F=A′B′D′+A′B′C′D′+A′BD+ABC′D with 8 or less literals.
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Realize a full subtractor using (i) only NAND gates and (ii) only NOR gates.
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Obtain the minimal expression using the tabular method and implement it in universal logic ⅀m(0,1,3,4,5,7,10,13,14,15)+d(2,6) and get the essential primes?
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Design a combinational circuit that accepts a 3-bit BCD number and generates an output binary number equal to the square of the input number.
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Realize the switching function F(A,B,C)=⅀m(2,4,5,6) by a hazard free logic gate network.
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Explain the following: (a) Race around condition in flip-flop (b) J-K master slave flip flop (c) Excitation tables for flip flops.
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Convert the T flip flop into (i) SR flip flop (ii) JK flip flop (iii) D flip flop
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Give the differences between Combinational and Sequential circuits based on their applications.
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Design a 3-bit counter which counts in the following sequence 0-2-5-3-4-0-2.
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Draw the state diagram and the state table for a 4-bit odd parity generator.
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Discuss the applications of shift registers? Design a parallel in serial out register?
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What do you mean by a parity bit generator? Explain its working with the help of a state diagram to generate odd parity?
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Get the ASM chart for Weighing Machine.
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Explain the procedure of the state minimization using the partition technique.
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Draw an ASM chart and state table for a 2-bit up-down counter having mode control input M=1 for Up counting, M=0 for down counting?
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What are the Moore and Mealy machines? Compare them.
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