JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV SYSTEM DESIGN USING FPGAS Previous Question Paper (July - 2021 - R16)
Answer any Five Questions. All Questions Carry Equal Marks.
Main
Design a T-flip flop using D-flip flop and implement the same in VHDL. Also draw the Schematic.
Answer
A T-flip flop can be designed using a D-flip flop by connecting the D-input to the XOR combination of the current state (Q) and the toggle input (T). The characteristic equation for a T-flip flop is Q(next) = T ⊕ Q. Since the characteristic equation for a D-flip flop is Q(next) = D, we set D = T ⊕ Q.
VHDL Implementation:
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity T_FF is
Port ( T, clk, rst : in STD_LOGIC;
Q : buffer STD_LOGIC );
end T_FF;
architecture Behavioral of T_FF is
signal D : STD_LOGIC;
begin
D <= T xor Q;
process(clk, rst)
begin
if rst = '1' then Q <= '0';
elsif rising_edge(clk) then Q <= D;
end if;
end process;
end Behavioral;Schematic Description: The schematic consists of a D-flip flop where the Q output is fed back through an XOR gate. The other input of the XOR gate is the T signal. The output of the XOR gate is connected to the D input of the flip flop.
Discuss the design of four, two input NAND gate using different VHDL statement. Also obtain the synthesized schematic for NAND gate.
Answer
To design a two-input NAND gate in VHDL, we can use different modeling styles: Dataflow, Behavioral, and Structural.
- Dataflow Modeling: Uses concurrent signal assignment.
Y <= not (A and B);process(A, B)
begin
if (A='1' and B='1') then Y <= '0';
else Y <= '1';
end if;
end process;U1: AND2 port map(A, B, temp);
U2: INV port map(temp, Y);Synthesized Schematic: Upon synthesis, the tool maps the logic to the target FPGA architecture. For a NAND gate, the schematic shows two input pins (A, B) connected to an AND gate symbol followed by an inverter (bubble) at the output, or a dedicated NAND gate primitive available in the FPGA's library.
Write the VHDL code for octal to binary encoder using RTL3 architecture. Also Synthesize the VHDL code.
Answer
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Synthesize equal VHDL code for all architectures N => 16. Compare the synthesis results.
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Design a 4-bit bidirectional shift register using RTL3 architecture. Also synthesize the VHDL code.
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Implement a 40-bit DMA starting word address register using VHDL.
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Implement the design of divided-by-3 clock divider circuit using VHDL code.
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Write the VHDL code for a counter controlled by enable signal and the flip flops do not have a gated clock input. List out the disadvantages of not having the gated clock.
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If the place and route tool has the clock synthesis capability, What are the changes that need to be done to VHDL code take advantage of it?
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In FIRCHIP plot I/O pads are placed on the boundary. The position of these I/O pads are certain to relate to the position of the package pins. What factors are to be considered for selecting a package for the design.
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Obtain the VHDL code for 4x1 Multiplexer using AND-OR gates along with schematic.
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Define a design directory structure for a design by two or more designers. State the assumptions, guidelines, usages, advantages and purposes.
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Design a 4-bit magnitude comparator using RTL4 architecture. Also draw the synthesized schematic for RTL4.
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A zero detector is similar to equality checker except that the constant has every bit '0'. Write VHDL code for zero detector and also synthesize the code.
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How can the data be transferred in an Universal Synchronous Transmitter and Receiver. Write the VHDL code and also draw the synthesized schematic. Also analyze the timing path required for each input.
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The functional vector for the fabrication vendor are required to test after fabrication. Develop a process to incorporate that format in to design environment.
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