JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV Year SYSTEM DESIGN USING FPGAS Previous Question Paper (June - 2024 - R16)
Note: i) Question paper consists of Part A, Part B. ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions. iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.
Part A
What components make up a synthesis environment?
Answer
A synthesis environment consists of three primary components: the HDL source code (such as Verilog or VHDL) which describes the design behavior, the technology library containing the target FPGA's specific logic cells and timing characteristics, and the synthesis tool (or compiler) which maps the high-level description into a netlist optimized for the selected hardware architecture.
How do pad characteristics affect signal integrity?
Answer
Pad characteristics significantly influence signal integrity by acting as the interface between the internal FPGA logic and the external PCB environment. Their impact is primarily governed by parasitic elements and impedance matching:
- Parasitic Capacitance and Inductance: The physical structure of a pad introduces parasitic capacitance and lead inductance. High capacitance can slow down signal transition times (rise/fall times), leading to increased propagation delay, while lead inductance can cause ground bounce and ringing during high-speed switching.
- Impedance Mismatch: If the pad's characteristic impedance does not match the transmission line impedance of the PCB trace, signal reflections occur. These reflections degrade the signal eye diagram and can cause data errors at high frequencies.
- Crosstalk: Poorly designed pad layouts or inadequate spacing can increase mutual capacitance and inductance between adjacent pads, leading to electromagnetic coupling and crosstalk, which introduces noise into sensitive signal paths.
Define the function of a leading zero circuit.
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What is the significance of a Barrel Shifter?
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How does the size and organization of registers affect the performance and capabilities of a microprocessor?
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What is the significance of configuration registers in digital systems?
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What are the advantages of having reset and clock circuitry in its own block separated from the rest of the circuits?
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What is gated clock and when it is used in digital designs?
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What is a netlist, and why is it important in digital design?
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What are some common issues or challenges addressed during post-layout verification?
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Part B
Discuss the key stages involved in an integrated design process.
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Write a VHDL code for three state buffers and draw the synthesized schematic for the three state buffer.
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In a synopsys VHDL simulation environment, how is the VHDL simulation library mapped? What are the advantages and disadvantages to share the working library for Synopsys VHDL simulation and synthesis tools?
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What is a Selector? Write VHDL code for Selector by modeling with a Process Statement.
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Write VHDL code to convert 4-bit binary code to a Gray code. Estimate the number of gates to be used. Synthesize the VHDL code.
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What is an Equality Checker? Write a Test Bench code to verify the correctness of the VHDL code of the Equality Checker.
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Design an 8-bit magnitude comparator using VHDL.
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Write the VHDL code for Signal Chopper along with the simulation waveform.
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What is an Asynchronous counter? Write the VHDL code for Asynchronous counter using JK Flip Flop and also draw the synthesized schematic.
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Outline the general framework for designing registers in digital systems, including key considerations from specification to implementation?
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Write a VHDL code for partitioning and synthesis of Register block along with synthesized schematic.
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Explain the significance of clock buffers in digital circuit design in reducing clock skew and enabling efficient clock distribution in complex digital systems.
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Describe the process of distributing the synthesized clock signal using VHDL code, including the instantiation of clock buffers and the creation of clock tree structures in the design.
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Write VHDL code to implement a skew scheduling algorithm for minimizing clock skew.
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Design a VHDL module for synchronizing data transfer between two clock domains.
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Explain how VHDL entities and architectures can be used for design partitioning.
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Write VHDL code representing a design entity and synthesize it using a synthesis tool like Synopsys Design Compiler.
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Describe the process of netlist generation from a high-level RTL design.
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Utilize VHDL timing constraints to perform worst-case timing analysis for critical paths in the design.
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