JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV Year SYSTEM DESIGN USING FPGAS Previous Question Paper (September - 2020 - R16)
Answer any five questions. All questions carry equal marks.
Main
Write Verilog module for a positive edge triggered flip-flop with test bench.
Answer
A positive edge-triggered D flip-flop is implemented using the always block sensitive to the rising edge of the clock signal. The Verilog module is defined as follows:
module d_ff(input clk, input d, output reg q);
always @(posedge clk) begin
q <= d;
end
endmoduleThe corresponding test bench to verify the functionality is:
module tb_d_ff;
reg clk, d; wire q;
d_ff uut(clk, d, q);
initial begin
clk = 0; forever #5 clk = ~clk;
end
initial begin
d = 0; #12 d = 1; #10 d = 0; #10 $finish;
end
endmoduleExplain JK Flip-flop implementation from VHDL code.
Answer
A JK flip-flop is implemented in VHDL by defining the state transition logic based on the inputs J and K. The behavior is modeled within a process block sensitive to the clock edge. The characteristic equation for a JK flip-flop is Q(next) = J(Q') + K'(Q).
The VHDL implementation structure is as follows:
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity jk_ff is
Port ( J, K, clk : in STD_LOGIC; Q : out STD_LOGIC);
end jk_ff;
architecture Behavioral of jk_ff is
signal q_int : STD_LOGIC := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if (J='0' and K='0') then q_int <= q_int;
elsif (J='0' and K='1') then q_int <= '0';
elsif (J='1' and K='0') then q_int <= '1';
else q_int <= not q_int;
end if;
end if;
end process;
Q <= q_int;
end Behavioral;Key implementation points include:
- The process block ensures sequential logic behavior triggered by the clock.
- The rising_edge(clk) function enforces the positive edge-triggering requirement.
- An internal signal q_int is used to store the current state, as output ports in VHDL cannot be read directly in all architectures.
- The conditional if-elsif structure maps the truth table of the JK flip-flop, including the toggle condition (J=1, K=1).
Draw Full Adder write a program gate level modeling.
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Write Verilog module for 4-bit comparator with test bench.
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Design Verilog module event construct for a serial data receiver and test bench for the same.
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Explain schematic diagram of shift register and draw the simulation waveform.
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Write the Verilog code for basic functional unit of a dynamic shift register.
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Explain synthesized schematic diagram of parallel to serial converter.
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Write the VHDL code to generate the divided-by-2 clocks.
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How can, correct the short path problem, explain with necessary diagram.
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What are the advantages of having reset and clock circuitry in its own block separated from the rest of the circuits?
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Explain, how gated clock signal to avoid generating a glitches in design.
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Mention the steps to be followed, when designing with FPGAs, a digital system.
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Why post layout verification is needed?
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What are the design trade-offs involving using additional flip-flops versus the serial of buffers?
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How Net List will be generated? Explain.
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