JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III Year ANALOG AND DIGITAL IC APPLICATIONS Previous Question Paper (February - 2022 - R16)

B.Tech | III Year | I Semester | R16 | February - 2022

Answer PaperPaper Code: 135BXMaximum Marks: 75Time: 3 hours

Answer any five questions. All questions carry equal marks.

Main

115 marks
a

What is an ideal active integrator? Explain its working with neat circuit diagram.

10 marks

Answer

An ideal active integrator is an operational amplifier circuit that performs the mathematical operation of integration on an input signal. It produces an output voltage that is proportional to the time integral of the input voltage. In this configuration, the feedback element is a capacitor, which allows the circuit to accumulate charge over time.

Circuit Diagram Description: The circuit consists of an Op-Amp with its non-inverting terminal connected to ground. The input signal Vin is connected to the inverting terminal through a resistor R. A capacitor C is placed in the feedback path between the output terminal and the inverting terminal.

Working Principle: Assuming the Op-Amp is ideal, the current flowing into the inverting terminal is zero due to infinite input impedance. Since the non-inverting terminal is at ground, the inverting terminal acts as a virtual ground. The current through the input resistor is:

I = Vin / R

This current must flow through the feedback capacitor C. The relationship between current and voltage for a capacitor is I = -C (dVout / dt). Equating the currents:

Vout = -(1 / RC) ∫ Vin dt + Vinitial

The negative sign indicates a 180-degree phase shift. The output is proportional to the integral of the input, scaled by the time constant τ = RC.

b

Explain the features of 741 Op-Amp.

5 marks

Answer

The 741 Op-Amp is a versatile, general-purpose integrated circuit. Its key features include:

  • High Open-Loop Gain: Typically around 200,000, allowing for precise control in feedback configurations.
  • Internal Frequency Compensation: It includes an internal 30pF capacitor that ensures stability and prevents oscillations without requiring external components.
  • Short-Circuit Protection: The output stage is designed to withstand short circuits to ground without damaging the device.
  • Offset Nulling Capability: It provides pins to connect an external potentiometer to null out any input offset voltage, ensuring zero output for zero input.
  • High Input Impedance: Typically 2 MΩ, which minimizes loading effects on the preceding signal source.
  • Low Output Impedance: Typically 75 Ω, allowing it to drive low-impedance loads effectively.
  • Common-Mode Rejection Ratio (CMRR): High CMRR (around 90 dB) ensures the device effectively rejects noise signals common to both inputs.
215 marks
a

Explain V to I converter using Op-Amp floating load and Op-Amp grounded load.

7 marks

Answer

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b

Design RC phase shift oscillator using op-amp and derive the necessary expression.

8 marks

Answer

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315 marks
a

Draw the circuit diagram of Schmitt trigger using op-amp and explain its operation with relevant waveforms.

10 marks

Answer

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b

Draw a circuit to for converting a square wave into a series of positive pulses.

5 marks

Answer

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415 marks
a

Draw the block diagram of monostable multivibrator using 555 timer and derive an expression for its frequency of oscillation.

10 marks

Answer

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b

List the applications of 565 PLL.

5 marks

Answer

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515 marks
a

With neat diagram, explain the working principle of R-2R ladder type DAC.

7 marks

Answer

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b

Explain successive approximation A/D converter.

8 marks

Answer

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615 marks
a

Design CMOS transistor circuit for 2-input AND gate. Explain the circuit with the help of function table.

8 marks

Answer

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b

Explain sinking current and sourcing current of TTL output. Which of the parameters decide the fan-out and how?

7 marks

Answer

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715 marks
a

Design a binary parallel adder/subtractor using 2’s complement system.

7 marks

Answer

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b

Design a Modulo-12 ripple counter using 74×74.

8 marks

Answer

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815 marks
a

Draw the basic cell structure of Dynamic RAM. What is the necessity of refresh cycle? Explain the timing requirements of refresh operation.

10 marks

Answer

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b

Give the differences between static and dynamic RAM.

5 marks

Answer

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About this paper

This page contains the question paper of ANALOG AND DIGITAL IC APPLICATIONS from JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD for B.Tech EEE III Year I Semester, February - 2022, R16.

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