JNTU B.Tech III ANALOG AND DIGITAL IC APPLICATIONS Previous Question Paper (October - 2020 - R16)

An Op-Amp integrator is designed by placing a capacitor C in the feedback path and a resistor R at the inverting input. To ensure stable operation and prevent DC offset saturation, a feedback resistor R_f is placed in parallel with the capacitor. The output voltage is given by v_o = -(1 / RC) ∫ v_i dt.

For a frequency range of 10 Hz to 1 KHz, the design steps are:

1. Select a capacitor C, typically in the range of 0.01 µF to 0.1 µF. Let C = 0.1 µF.
2. Determine the time constant RC based on the lowest frequency (f_a = 10 Hz). To ensure integration occurs at this frequency, set the corner frequency f_b = 1 / (2πR_fC) to be lower than the input frequency.
3. Choose R such that the gain is manageable; for unity gain at a specific frequency, R = 1 / (2πfC).
4. Connect a resistor R_f = 10R in parallel with C to provide a DC feedback path, which limits the gain at low frequencies and prevents output drift.

An instrumentation amplifier is designed using three op-amps to provide high input impedance and high common-mode rejection ratio (CMRR). The circuit consists of two stages: a differential input stage using two non-inverting amplifiers and a second stage using a differential amplifier.

The design configuration is as follows:

1. The first stage uses two op-amps with inputs connected to their non-inverting terminals. A gain-setting resistor R_g is connected between the inverting terminals of these two op-amps.
2. The output of the first stage is v_o1 = (1 + 2R₁ / R_g)(v₂ - v₁), where R₁ are the input stage resistors.
3. The second stage is a standard differential amplifier with four equal resistors R₂, providing a gain of 1.
4. The total voltage gain is A_v = (1 + 2R₁ / R_g).
5. By adjusting R_g, the gain can be varied without affecting the CMRR of the circuit.