JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III COMPUTER ARCHITECTURE Previous Question Paper (August - 2022 - R18)

A general computer system architecture consists of three primary components: the Central Processing Unit (CPU), Memory Unit, and Input/Output (I/O) System, all interconnected via a system bus. The CPU acts as the brain, executing instructions through its Control Unit (CU) and Arithmetic Logic Unit (ALU). The Memory Unit stores programs and data, while the I/O system facilitates communication with external devices.

The architecture is structured around the system bus, which comprises the data bus, address bus, and control bus. The address bus transmits the location of data, the data bus carries the actual information, and the control bus manages the timing and coordination between units. This organization follows the Von Neumann model, where instructions and data reside in the same memory space.

Hardware implementation of a CPU using micro-instructions is known as microprogrammed control. In this approach, the control unit is designed as a small, high-speed memory called the Control Memory (CM), which stores microprograms. Each machine instruction is broken down into a sequence of micro-operations, represented as micro-instructions.

Key components include:

1. Control Address Register (CAR): Holds the address of the next micro-instruction to be read from the control memory.
2. Control Buffer Register (CBR): Holds the micro-instruction currently being executed.
3. Sequencer (Next Address Generator): Determines the address of the next micro-instruction based on the current instruction, status bits, and branch conditions.

When an instruction is fetched, the opcode is mapped to the starting address of the corresponding microprogram in the control memory. The micro-instructions are then executed sequentially, generating control signals that dictate the operations of the ALU, registers, and data paths. This design offers flexibility, as changing the instruction set only requires updating the contents of the control memory rather than reconfiguring physical hardware logic.