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JNTU B.Tech IV VLSI DESIGN Previous Question Paper (July - 2021 - R16)

B.Tech | IV | I | R16 | July - 2021

Answer PaperPaper Code: 137JDMaximum Marks: 75Time: 3 Hours

Answer any Five Questions. All Questions Carry Equal Marks.

Main

1

Evaluate the DC transfer characteristics of CMOS inverter.

15 marks

Answer

The DC transfer characteristics of a CMOS inverter describe the output voltage (Vout) as a function of the input voltage (Vin). The curve is divided into five distinct regions of operation based on the conduction states of the nMOS and pMOS transistors.

  1. Region 1 (Vin < Vtn): The nMOS is in cutoff (OFF) and the pMOS is in the linear region (ON). Since no current flows, Vout = VDD.
  2. Region 2 (Vtn ≤ Vin < VDD/2): The nMOS turns on and enters saturation, while the pMOS remains in the linear region. Vout begins to drop from VDD.
  3. Region 3 (Vin = VDD/2): Both transistors are in saturation. This is the transition region where the slope is steepest. The switching threshold voltage VM is defined where Vin = Vout.
  4. Region 4 (VDD/2 < Vin ≤ VDD - |Vtp|): The nMOS is in the linear region and the pMOS enters saturation. Vout continues to decrease.
  5. Region 5 (Vin > VDD - |Vtp|): The pMOS is in cutoff (OFF) and the nMOS is in the linear region. Vout = 0V.

The switching threshold VM is given by the expression:

VM = (Vtn + sqrt(kp/kn) * (VDD - |Vtp|)) / (1 + sqrt(kp/kn))

where kn and kp are the transconductance parameters of the nMOS and pMOS transistors respectively. For a symmetric inverter where kn = kp and Vtn = |Vtp|, the switching threshold is exactly VDD/2, providing maximum noise margins and optimal switching performance.

2

Derive the drain current of MOS device in different operating regions.

15 marks

Answer

The drain current ID of an n-channel MOSFET is derived based on the charge induced in the channel by the gate voltage and the drift velocity of carriers under the influence of the lateral electric field.

The charge per unit area in the channel at a distance x from the source is given by:

Qch(x) = -Cox(VGS - VT - V(x))

where Cox is the gate oxide capacitance per unit area, VGS is the gate-to-source voltage, VT is the threshold voltage, and V(x) is the channel potential at x. The drain current is defined by the drift equation:

ID = -W μn Qch(x) dV(x)/dx

Substituting Qch(x) and integrating from x=0 (where V=0) to x=L (where V=VDS):

∫0L ID dx = W μn Cox ∫0VDS (VGS - VT - V) dV

1. Linear (Triode) Region (VGS - VT > VDS):

Performing the integration yields the linear current equation:

ID = μn Cox (W/L) [(VGS - VT)VDS - (VDS2/2)]

2. Saturation Region (VGS - VT ≤ VDS):

As VDS increases to VGS - VT, the channel at the drain end pinches off. The current becomes independent of VDS. Substituting VDS = VGS - VT into the linear equation:

ID = (1/2) μn Cox (W/L) (VGS - VT)2

3. Cut-off Region (VGS < VT):

When the gate voltage is below the threshold voltage, no inversion layer is formed, and the drain current is negligible:

ID ≈ 0
3

With necessary illustrations explain the layout design rules and draw the layout diagram for four input NAND gate.

15 marks

Answer

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4

Explain in detail about the need of scaling, scaling principles and effect of scaling on MOSFET device parameters.

15 marks

Answer

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5

Derive the expression for time delay of a MOS device with cascaded inverters as drivers.

15 marks

Answer

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6

Examine the concept of carry look ahead adder and discuss its advantages and disadvantages.

15 marks

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7

Define shifter and give a short note on

15 marks
a

Barrel shifter.

7 marks

Answer

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b

Logarithmic shifter.

8 marks

Answer

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8

Explain the various design strategies for test.

15 marks

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