JNTU
JNTU B.Tech IV VLSI DESIGN Previous Question Paper (May/June - 2019 - R15)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit.
Part A
What are the two additional layers in BiCMOS technology?
Answer
The two additional layers required in BiCMOS technology compared to standard CMOS are the N-well (or N-epitaxial layer) to house the PNP transistor and the P-base (or P-type diffusion) region for the NPN transistor base.
Define gm, VTH and gds of MOSFET.
Answer
gm (Transconductance): The change in drain current per unit change in gate-source voltage, representing the gain of the MOSFET.
VTH (Threshold Voltage): The minimum gate-to-source voltage required to create a conducting channel between the source and drain.
gds (Drain Conductance): The inverse of the output resistance, representing the change in drain current per unit change in drain-source voltage in the saturation region.
What are the different scaling factors there in the design of VLSI?
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What are the advantages of multi layers over single layer?
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List different gate level design logics.
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What is mean by fan-in and fan-out?
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What is serial access memory?
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What is zero counter detectors?
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Compare PLA and PAL.
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Define stuck–at-0/1 faults with examples.
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Part B
Explain the fabrication steps of PMOS technology with neat diagrams.
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What is latch up? How to overcome it?
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Derive the pull up to pull down ratio of inverter driving another inverter.
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What is stick diagram? What are the applications of it? How it is used in VLSI design? Draw the stick diagram for nMOS inverter.
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What are the different types of design rules? Explain their significance in VLSI design.
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Draw the layout of CMOS NOR gate and explain how to understand it.
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Draw the logic diagram of dynamic NAND gate and explain its working with truth table and also compare its performance with other logic gates.
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How to drive the large capacitive loads? Explain any one of such method in detail with neat diagrams.
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Design Parity generator and draw its logic diagram and layout and also explain its working.
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Design SRAM and draw its circuit diagram and layout and also explain how it stores bits.
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What are the different parameters that are influence on the low power design?
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How FPGAs are used in VLSI design? Explain what are the advantages of it over CPLDs?
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What are the techniques are available to test a chip? Explain them in detail.
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