JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III VLSI DESIGN Previous Question Paper (April - 2018 - R15)
Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question in Part B carries 10 marks.
Part A
Answer all questions.
Define figure of merit of MOS transistor.
Answer
The figure of merit of a MOS transistor is defined as the ratio of transconductance to the gate capacitance, representing the device's switching speed capability. It is given by the formula:
where gₘ is the transconductance and C_g is the gate capacitance.
Draw the CMOS inverter circuit.
Answer
A CMOS inverter consists of a PMOS transistor connected between the supply voltage (V_DD) and the output, and an NMOS transistor connected between the output and ground (V_SS), with both gates tied together as the input.
V_DD
|
[PMOS]
|
Input --+-- Output
|
[NMOS]
|
GNDWhat is meant by synthesis?
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Differentiate Functional simulation and timing simulation.
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What is the importance of fan-in and fan-out?
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Differentiate rise time and fall time.
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Draw the 1-bit SRAM cell.
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What are the various serial access memories?
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Implement 2:1 MUX using PAL.
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What is the difference between verification and validation?
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Part B
Draw and explain the operation of BiCMOS inverter.
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Derive the drain to source current equation for NMOS enhancement mode transistor.
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Discuss the steps involved in VLSI design flow.
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Draw the stick diagram for the following Boolean expression using CMOS logic.
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Briefly explain the commonly used technique to estimate the delay time of a MOS inverter.
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Implement 4:1 multiplexer using switch logic.
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Design a 4-bit magnitude comparator.
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Design a zero detector circuit.
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Discuss scan design Techniques.
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Compare various programmable devices.
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