JNTU
JNTU B.Tech III VLSI DESIGN Previous Question Paper (December - 2018 - R15)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
PART - A
Write about the Pass transistor.
Answer
A pass transistor is a MOSFET used as a switch to pass a signal from its source to its drain. It is controlled by a gate voltage; when the gate voltage is high (for NMOS), the transistor conducts, allowing the signal to pass, and when low, it acts as an open circuit.
Distinguish between Enhancement and Depletion mode transistor action in N-MOS.
Answer
An Enhancement mode transistor is normally off and requires a positive gate-to-source voltage (Vgs > Vt) to create a conducting channel. A Depletion mode transistor has a pre-implanted channel, making it normally on; it requires a negative gate-to-source voltage to turn off by depleting the channel of carriers.
Write about contacts and vias in layout design.
Answer
Sign in to view the complete answer paper.
Write about the 1.2 μm double metal single poly CMOS rules.
Answer
Sign in to view the complete answer paper.
Mention the different forms of Time delays in gate level circuits.
Answer
Sign in to view the complete answer paper.
Explain about Switch logic and its usage.
Answer
Sign in to view the complete answer paper.
Distinguish a synchronous and an asynchronous counters.
Answer
Sign in to view the complete answer paper.
Write a note on Content Addressable Memory.
Answer
Sign in to view the complete answer paper.
What is the need for testing of IC?
Answer
Sign in to view the complete answer paper.
What are the different chip-level Test Techniques?
Answer
Sign in to view the complete answer paper.
PART - B
Explain the CMOS fabrication process in p-well using suitable diagrams.
Answer
Sign in to view the complete answer paper.
Discuss the effect of threshold voltage on MOSFET current Equations.
Answer
Sign in to view the complete answer paper.
Discuss the MOS transistor Characteristics in Depletion and enhancement modes.
Answer
Sign in to view the complete answer paper.
Write about Alternative forms of pull-up and describe about the NMOS pull-ups.
Answer
Sign in to view the complete answer paper.
Write about the stick diagrams and design a stick diagram for two input N-MOS NAND and NOR gates.
Answer
Sign in to view the complete answer paper.
Distinguish between the Lambda-base rules and Double metal MOS process rules.
Answer
Sign in to view the complete answer paper.
Draw the neat layout diagrams for NMOS shift register cell.
Answer
Sign in to view the complete answer paper.
Explain the formal estimation of CMOS inverter delay rise-time estimation and Fall-time estimation.
Answer
Sign in to view the complete answer paper.
Write a note on the Wiring capacitance in detail.
Answer
Sign in to view the complete answer paper.
Write about the different Alternate gate circuits in detail.
Answer
Sign in to view the complete answer paper.
Discuss about the Choice of layers for the gate level design.
Answer
Sign in to view the complete answer paper.
Explain the working principle of Ripple carry adder using Transmission Gates.
Answer
Sign in to view the complete answer paper.
Explain about the configurations and applications of SRAM and DRAM cells.
Answer
Sign in to view the complete answer paper.
Explain the Principle and structure of Serial-Parallel multiplier.
Answer
Sign in to view the complete answer paper.
Describe the design procedure for design of a asynchronous counter.
Answer
Sign in to view the complete answer paper.
Design a PAL to realize a full Adder circuit.
Answer
Sign in to view the complete answer paper.
Explain the detailed Architecture of CPLD and its Implementations.
Answer
Sign in to view the complete answer paper.
Write a short note on the following:
CMOS Testing
Answer
Sign in to view the complete answer paper.
Strategies for testing.
Answer
Sign in to view the complete answer paper.