JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (May - 2018 - R15)
Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks.
Part A
What is gray code? List 4-bit gray code for decimal 0 to 3.
Answer
Gray code is an unweighted binary number system where successive values differ in only one bit position. The 4-bit Gray code for decimal 0 to 3 is: 0 (0000), 1 (0001), 2 (0011), 3 (0010).
What is Excess-3 code? Find the 9’s complement of decimal number 57.
Answer
Excess-3 code is a non-weighted BCD code obtained by adding 3 to each decimal digit before converting it to binary. The 9's complement of 57 is calculated by subtracting each digit from 9: 9-5=4 and 9-7=2, resulting in 42.
What is a multiplexer?
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Discuss briefly about Tristate bus system.
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What is the function of a D-Flip flop?
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Distinguish between combinational and sequential switching circuits.
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What are the different types of shift registers?
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What are the advantages and disadvantages of ripple counters?
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What is a Mealy machine?
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What is an ASM chart?
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Unit I
What are error detecting codes? Give examples. What are the drawbacks of error detecting codes.
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Draw the logic symbols of all basic logic gates indicating the output expression and write the truth tables.
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Unit II
Define the following terms with respect to K-Map: i) Prime implicant, ii) Essential Prime implicants. Reduce using K-maps the expression f = ∑m(0,1,2,3,5,7,8,9,10,12,13) and implement the real minimal expression using NAND gates.
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Design a 4-bit adder circuit using logic gates. Draw the diagram of 1-bit comparator using logic gates and explain.
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Unit III
Draw the logic diagram of a master slave JK flip flop using NAND gates and explain its truth table. Define the following with respect to flip flops: i) Set-up time, ii) Hold time.
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Explain the conversion of JK flip flop to SR flip flop. Give the applications of flip flops.
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Unit IV
Design a synchronous Mod-6 counter using JK flip flops.
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Explain the approaches to the design of synchronous sequential Finite State Machines. Design the sequential circuit with D flip flops for the provided state diagram.
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Unit V
Find the equivalence partition and a corresponding reduced machine in standard form for the machine given in table.
| PS | NS, Z (X=0) | NS, Z (X=1) |
|---|---|---|
| A | B, 0 | E, 0 |
| B | E, 0 | D, 0 |
| C | D, 1 | A, 0 |
| D | C, 1 | E, 0 |
| E | B, 0 | D, 0 |
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Draw an ASM chart to design a binary multiplier control. Design the control using D-flip flops and Decode logic.
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