JNTU B.Tech III DIGITAL SYSTEM DESIGN Previous Question Paper (February - 2023 - R16)

What is a Sequential Machine?

What are the limitations of Finite State Machines?

What is meant by State graph?

What are the differences between ROM, PLA and PAL?

How can a State Graph be converted in to SM chart?

What is the difference between an SM chart and ordinary flow chart?

What is meant by Fault Dominance?

What is meant by Transition count testing?

Define Singleton.

What is meant by Homing Tree?

With a neat block diagram, explain the Finite State Model

Examine the possibility of hazard in the OR-AND logic circuit whose Boolean function is given by f= Σ(0,2, 6,7). Show how the hazard can be detected and eliminated.

Investigate the menace of races that occur in ASC and its types with the aid of appropriate transition diagrams or flow diagrams. Specify the notion of cycle.

Explain the procedure of state minimization using the partition technique.

A sequential circuit has one input (X) and two outputs (Z1 and Z2). An output Z1 = 1 occurs every time the input sequence 100 is completed, provided that the sequence 010 has never occurred. An output Z2 = 1 occurs every time the input sequence 010 is completed. Note that once a Z2 = 1 output has occurred, Z1 = 1 can never occur but not vice versa. Find a Mealy state graph and table.

Obtain the state graph and state table for Score Board and Controller.

A sequential circuit has an input (X) and outputs (Y and Z). YZ represents a 2-bit binary number equal to the number of 1’s that have been received as inputs. The circuit resets when the total number of 1’s received is 3, or when the total number of 0’s received is 3. Find a Moore state graph and table for the circuit.

Implement the following functions using PLA and obtain their compatibility matrix. f1(a,b,c,d) = Σ(1,2,3,4,5,6,8,10,13,15) f2(a,b,c,d) = Σ(2,9,10,12,14,15)

Construct an SM block that has three input variables (D, E, F), four output variables (P, Q, R, S) and two exit paths. For this block, output P is always 1, and Q is 1 if D = 1. If D and F are 1 or if D and E are 0, R = 1 and exit path 2 is taken. If (D = 0 and E = 1) or (D = 1 and F = 0), S = 1 and exit path 1 is taken.

Describe the components of SM charts and illustrate with an example.

Describe the realization of Binary Divider using PLA and Flip Flops.

Obtain the state graph for a Dice Game Controller with a neat sketch.

Describe PODEM algorithm in detail. Also explain how PODEM algorithm overcomes the drawback of D-Algorithm.

Let N be a combinational circuit composed of only NAND gates. Assume that every primary has only one fanout. Show that a test set that detects all s-a-1 faults in N detects all s-a-0 faults.

Describe Kohavi Algorithm for multiple fault detection.

Explain in detail about Signature Analysis and Test Bridging Faults.

Describe the Transition Check Approach used for Test generation of Sequential Logic Circuits.

For the following machine define distinguishing sequence.