JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III Year DIGITAL SYSTEM DESIGN Previous Question Paper (July - 2023 - R16)

B.Tech | III Year | II Semester | R16 | July - 2023

Answer PaperPaper Code: 136BFMaximum Marks: 75Time: 3 Hours

Note: i) Question paper consists of Part A, Part B.
ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions.
iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.

Part A

1.a

State the concept of state equivalence in sequential machines and its importance in machine minimization.

2 marks

Answer

Two states, Si and Sj, of a sequential machine are defined as equivalent if and only if for every possible input sequence, the machine produces the same output sequence regardless of whether it starts in state Si or Sj. If two states are equivalent, they are indistinguishable in terms of their future behavior.

This concept is fundamental to machine minimization because it allows for the identification and merging of redundant states. By replacing a set of equivalent states with a single representative state, the total number of states in the state table can be reduced, leading to a simpler, more efficient circuit implementation with fewer flip-flops and reduced combinational logic complexity.

1.b

Describe the process of simplifying incompletely specified machines, including the steps involved and the techniques used.

3 marks

Answer

The process of simplifying an incompletely specified machine involves finding the minimum number of states required to represent the same input-output behavior. Since some transitions or outputs are unspecified (don't-care conditions), the states are considered compatible rather than equivalent.

  1. Identify Compatible States: Two states are compatible if, for every input, their outputs are identical whenever both are specified, and their next states are either identical or also compatible.
  2. Find Maximal Compatibles: Construct a compatibility graph or table to identify all sets of states that are pairwise compatible. A set is a maximal compatible if no other state can be added to it while maintaining pairwise compatibility.
  3. Form a Minimum Closed Cover: Select a minimum number of maximal compatibles such that every state of the original machine is included in at least one chosen compatible (covering) and the set of chosen compatibles is closed under the next-state transition (closure).

This simplification is typically performed using the Partitioning Method or by constructing a Compatibility Table to systematically eliminate redundant states.

1.c

Define state graphs and their role in control circuits.

2 marks

Answer

Sign in to view the complete answer paper.

1.d

Describe the purpose and function of a BCD adder in digital arithmetic.

3 marks

Answer

Sign in to view the complete answer paper.

1.e

Define state machine charts and their role in digital systems design.

2 marks

Answer

Sign in to view the complete answer paper.

1.f

Discuss the process of deriving state machine charts from a given problem statement.

3 marks

Answer

Sign in to view the complete answer paper.

1.g

What is the significance of bridging fault model?

2 marks

Answer

Sign in to view the complete answer paper.

1.h

Compare and contrast multiple stuck-at fault models with the single stuck-at fault model.

3 marks

Answer

Sign in to view the complete answer paper.

1.i

Define the circuit test approach for fault diagnosis in sequential circuits.

2 marks

Answer

Sign in to view the complete answer paper.

1.j

Elaborate on the components of a fault detection experiment in sequential circuits and their functions.

3 marks

Answer

Sign in to view the complete answer paper.

Part B

2

Analyze an incompletely specified machine and identify redundant states or transitions that can be eliminated without affecting the desired functionality. Present the original machine and the optimized version, clearly illustrating the simplification process (figure 1).

10 marks

Answer

Sign in to view the complete answer paper.

OR
310 marks
a

Explain Mealy and Moore model of a clocked synchronous sequential network.

5 marks

Answer

Sign in to view the complete answer paper.

b

What is Finite State Machine? Describe the Capabilities and limitations of finite-state machine.

5 marks

Answer

Sign in to view the complete answer paper.

4

Design a 32-bit adder using ripple-carry adders. Present the block diagram and the corresponding logic equations for the adder.

10 marks

Answer

Sign in to view the complete answer paper.

OR
5

Design a digital circuit that incorporates ROMs, PALs, or PLAs to implement a complex arithmetic operation, such as a floating-point multiplier. Present the block diagram, truth tables, and logic equations for the circuit.

10 marks

Answer

Sign in to view the complete answer paper.

6

Derive a state machine chart for a traffic light controller that efficiently manages the flow of vehicles at an intersection, considering different traffic patterns and pedestrian signals.

10 marks

Answer

Sign in to view the complete answer paper.

OR
710 marks
a

Compare different implementations of a binary multiplier, such as array multipliers, booth encoding.

5 marks

Answer

Sign in to view the complete answer paper.

b

Evaluate the functionality and reliability of a dice game controller implemented using a state machine chart.

5 marks

Answer

Sign in to view the complete answer paper.

810 marks
a

With an example, explain the procedure involved in the path sensitization technique.

5 marks

Answer

Sign in to view the complete answer paper.

b

What is the significance of Kohavi algorithm? Explain how it is useful in the detection of faults in digital circuits.

5 marks

Answer

Sign in to view the complete answer paper.

OR
910 marks
a

Draw the table giving the set of all possible single struck faults and the faulty and fault-free responses and also construct the fault cover table for the circuit in figure 2.

5 marks

Answer

Sign in to view the complete answer paper.

b

Analyze the concept of fault dominance in digital circuits. Discuss the conditions under which a fault is dominant over another fault.

5 marks

Answer

Sign in to view the complete answer paper.

1010 marks
a

Explain the different types of fault diagnosis methods in sequential circuits.

5 marks

Answer

Sign in to view the complete answer paper.

b

Explain the procedure of designing a fault detection experiment with the help of an example.

5 marks

Answer

Sign in to view the complete answer paper.

OR
11

Explain in detail about state Identification experiment and fault detection experiment.

10 marks

Answer

Sign in to view the complete answer paper.

About this paper

This page contains the question paper of DIGITAL SYSTEM DESIGN from JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD for B.Tech ECE III Year II Semester, July - 2023, R16.

For the solved question paper with answers, switch to the Answer Paper tab.

Other papers in DIGITAL SYSTEM DESIGN

Loading Question Papers

Fetching data from database...