JNTU
JNTU B.Tech III Year DIGITAL SYSTEM DESIGN Previous Question Paper (February/March - 2022 - R16)
Answer any five questions. All questions carry equal marks.
Main
Draw the state flow or transition diagram for a JK flip-flop and also give the truth table associated with it.
Answer
The JK flip-flop state transition diagram consists of four states representing the output Q, controlled by inputs J and K. The transitions are defined as follows: if J=0, K=0, the state remains unchanged (Q to Q); if J=0, K=1, the state resets to 0; if J=1, K=0, the state sets to 1; if J=1, K=1, the state toggles (Q to Q').
| J | K | Q(n) | Q(n+1) | Operation |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | No Change |
| 0 | 0 | 1 | 1 | No Change |
| 0 | 1 | 0 | 0 | Reset |
| 0 | 1 | 1 | 0 | Reset |
| 1 | 0 | 0 | 1 | Set |
| 1 | 0 | 1 | 1 | Set |
| 1 | 1 | 0 | 1 | Toggle |
| 1 | 1 | 1 | 0 | Toggle |
What are the limitations of Finite State Machines?
Answer
Finite State Machines (FSMs) face several limitations in practical digital design:
- State Explosion: As the complexity of the system increases, the number of states grows exponentially, making the design, verification, and implementation of the state transition table difficult.
- Memory Constraints: FSMs rely on flip-flops for state storage; large state machines require significant hardware area for registers and combinational logic.
- Performance Bottlenecks: The sequential nature of FSMs limits throughput, as the clock frequency is constrained by the critical path through the combinational logic between states.
- Rigidity: FSMs are hard-wired and difficult to reconfigure or update once implemented in hardware compared to software-based approaches.
What is a Hazard? Differentiate between Static Hazard and Dynamic Hazard.
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Obtain a flow table that meets the following requirements: 1) There are two inputs x1 and x2 and a single output z. 2) The inputs x1 and x2 never change simultaneously. 3) The output is to be 1 every other time the input is x1x2 = 10; otherwise the output is set to be 0.
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Design a finite state machine (FSM) that will detect more than one number 1's, in the previous three samples. For example Input Sequence 0101011001 and Output Sequence 0001011100.
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Draw the block diagram of a parallel binary divider and obtain the state graph for divider control circuit.
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Design and draw state graph for Keyboard Scanner.
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Realize a 4-bit BCD to gray code converter using PLA.
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Describe the overview of scoreboard controller and also explain the state graph for score board controller.
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Realize the state machine chart for dice controller with block diagram and state diagram.
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What is the relation between State diagram and SM chart? Explain with an example.
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Draw and explain different components of an SM chart.
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Construct a SM block for state S1 that has two input variables x1 and x2 along with two output variable, z1 and z2. The output z1 is always asserted and the output z2 is asserted if x1 = 1. If x1 = 0, then the system is to remain in state S1. Otherwise if x2 = 0, then block exits to state S2 and if x2 = 1, the block exits to state S3.
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Describe Kohavi algorithm with an example.
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Draw the architecture of built in Self-Test and explain its operation.
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Give the detailed procedure of Transition check approach of sequential circuits.
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Explain the circuit test approach concept in sequential circuits.
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