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JNTU B.Tech III DIGITAL SYSTEM DESIGN Previous Question Paper (January/February - 2021 - R16)

B.Tech | III | II | R16 | January/February - 2021

Answer PaperPaper Code: 136BFMaximum Marks: 75Time: 2 hours

Answer any five questions. All questions carry equal marks.

Main

1

For the machine given below find the equivalence part and a corresponding reduced machine in standard form.

PSNS,Z (X=0)NS,Z (X=1)
AB,0E,0
BE,0D,0
CD,1A,0
DC,1E,0
EB,0D,1
15 marks

Answer

To find the equivalence partition, we identify states that produce the same output and transition to equivalent next states. We start by partitioning states based on their outputs (Z) for inputs X=0 and X=1.

Step 1: Initial Partition (P0)
Group states by output Z: S0 = {A, B, E}, S1 = {C, D}.

Step 2: First Iteration (P1)
Check transitions for states in {A, B, E}:
For A: X=0 → B (S0), X=1 → E (S0)
For B: X=0 → E (S0), X=1 → D (S1)
For E: X=0 → B (S0), X=1 → D (S1)
Since A transitions to different partitions than B and E, we split: P1 = {A}, {B, E}, {C, D}.

Step 3: Second Iteration (P2)
Check transitions for {B, E}:
For B: X=0 → E (in {B, E}), X=1 → D (in {C, D})
For E: X=0 → B (in {B, E}), X=1 → D (in {C, D})
Since B and E have identical transitions, they are equivalent. Check {C, D}:
For C: X=0 → D (in {C, D}), X=1 → A (in {A})
For D: X=0 → C (in {C, D}), X=1 → E (in {B, E})
Since D transitions to E (in {B, E}) for X=1, while C transitions to A (in {A}), C and D are not equivalent. Thus, P2 = {A}, {B, E}, {C}, {D}.

Reduced Machine Table:
Let state G = {B, E}.

PSNS,Z (X=0)NS,Z (X=1)
AG,0G,0
GG,0D,1
CD,1A,0
DC,1G,1
2

Explain the various types of hazards in sequential circuit design and the methods to eliminate them. Give suitable examples.

15 marks

Answer

Hazards in sequential circuits are unwanted switching transients that occur when different paths in a circuit have different propagation delays, potentially leading to incorrect state transitions or output glitches. In sequential logic, these are broadly categorized into static, dynamic, and essential hazards.

1. Static Hazards: Occur when the output should remain constant but momentarily changes due to a single input transition. A static-1 hazard occurs if the output momentarily drops to 0, while a static-0 hazard occurs if it rises to 1. These are typically caused by race conditions in combinational logic driving the flip-flop inputs.

2. Dynamic Hazards: Occur when the output is supposed to change from 0 to 1 or 1 to 0 but changes multiple times before settling at the final value. This is caused by the presence of multiple paths with varying delays between the input and output.

3. Essential Hazards: Unique to sequential circuits, these occur when a change in an input variable causes a change in the state of the circuit, but due to unequal delays in the feedback paths, the circuit enters an incorrect state. This is common in asynchronous sequential circuits where the feedback loop delay is shorter than the input signal propagation delay.

Methods to Eliminate Hazards:

  • Adding Redundant Logic: For static hazards in combinational parts, adding redundant prime implicants (consensus terms) in the K-map ensures that the circuit remains covered during input transitions. For example, in the function F = AB + A'C, adding the term BC covers the transition between AB and A'C, eliminating the hazard.
  • Delay Elements: Inserting buffers or delay elements in feedback paths ensures that the state variables change only after the input signals have stabilized, effectively mitigating essential hazards.
  • Synchronous Design: The most robust method is to use a global clock signal. By ensuring that all state changes occur only on the edge of the clock (using edge-triggered flip-flops), the circuit ignores transient glitches that occur between clock edges.
  • Hazard-Free State Assignment: In asynchronous design, using specific state assignment techniques (like Gray coding) ensures that only one state variable changes at a time, preventing critical races that lead to hazards.
315 marks
a

With a neat block diagram explain the design of a keypad scanner.

8 marks

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b

With a neat block diagram explain the operation of read only memories.

7 marks

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4

Realize the following functions using 3x5x4 PL. Write AND-OR array equivalent circuit.

F0 = Σm(0,1,4,6)
F1 = Σm(2,3,4,6,7)
F2 = Σm(0,1,2,6)
F3 = Σm(2,3,5,6,7)
15 marks

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515 marks
a

Describe how to convert a state graph into an SM chart.

8 marks

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b

Explain in detail about linked state machines.

7 marks

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6

Derive an SM chart for a binary multiplier.

15 marks

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715 marks
a

Determine using boolean difference method the test vectors for SA0 faults and SA1 faults on all input lines of the circuit that is to realize the function:

w = x1 . x4 + x2 . x3 + x4 . x1
8 marks

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b

Discuss about different types of faults in digital circuits.

7 marks

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8

Explain the concept Fault detection and location in Sequential circuits with an example.

15 marks

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This page contains the question paper of DIGITAL SYSTEM DESIGN from JNTU for B.Tech ECE III II, January/February - 2021, R16.

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