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JNTU B.Tech II STRUCTURED DIGITAL SYSTEM DESIGN Previous Question Paper (December - 2017 - R15)

B.Tech | II | II | R15 | December - 2017

Answer PaperPaper Code: 124DRMaximum Marks: 75Time: 3 Hours

Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks.

Part A

125 marks
a
Define the terms Information and Binary logic.
2 marks

Answer

Information is the meaningful data or knowledge represented in a system, while Binary logic is a system of logic that operates on two distinct values, typically represented as 0 and 1, true and false, or low and high voltage levels.

b
Using ASSERTED and other phraseology, describe the general AND and OR gates?
3 marks

Answer

An AND gate is asserted (high) if and only if all its input signals are asserted simultaneously. An OR gate is asserted if at least one of its input signals is asserted.

c
Define fan-in, fan-out and standard load.
2 marks

Answer

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d
What is a tri-state buffer?
3 marks

Answer

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e
What is the difference between a sequential machine and a finite state machine?
2 marks

Answer

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f
List the two essential properties a digital system must have in order to be classed as a sequential circuit.
3 marks

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g
Define the state of the machine.
2 marks

Answer

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h
What are the applications of ring counters?
3 marks

Answer

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i
What is meant by SISO-SIPO?
2 marks

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j
How a shift register can be used to derive the twisted ring counter?
3 marks

Answer

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Unit I

210 marks
a
Explain the implementation procedure in hardware for the following expression:
F = A.B + A'.C
5 marks

Answer

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b
Design a four bit parity checker that is, a circuit that can be used to check parity over a five bit word as well as generate the parity bit over a four bit word.
5 marks

Answer

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OR
310 marks
a
Implement the following Boolean function using only one 7442 (BCD to decimal decoder with LOW ASSERTED outputs) and some extra gates:
F(A,B,C,D) = ABC'+AB'+B'C
5 marks

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b
Draw the block diagram of a two bit comparator and explain its working with truth-table and also write its equation.
5 marks

Answer

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Unit II

410 marks
a
Draw the schematic symbol for a wired OR network and also draw its wired OR circuit.
5 marks

Answer

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b
Explain the concept of current flow for a wired logic circuit when the bus wire is HIGH.
5 marks

Answer

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OR
510 marks
a
Draw the black box model of the general logic device and explain it in terms of loading concept.
5 marks

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b
Determine the propagation delay through an inverter with neat illustrations.
5 marks

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Unit III

610 marks
a
Explain the working of a finite machine with general modal diagram.
5 marks

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b
How the sequential circuits are classified? Explain them.
5 marks

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OR
710 marks
a
Draw the circuit diagram of RC oscillator and explain its working and also write its advantages and disadvantages.
5 marks

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b
Convert the RS flip-flop to a T-Latch and explain them with truth table.
5 marks

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Unit IV

810 marks
a
Explain the procedure for developing the hardware for the NEXT STATE DECODER.
5 marks

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b
Explain the process of state reduction to recovering errors incurred during the state diagram design.
5 marks

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OR
9
Design a synchronous finite state machine which will sequence from state a=00 to state b=11 to state c=10 to state d=01, then reverse itself at state ‘a’ and state ‘d’ if the input COSQ(H) is ASSERTED. Any time the COSQ input is NOT ASSERTED the circuit is to revert to state a and hold. Carry out all steps for the design.
10 marks

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Unit V

10
Design modulo 8 Gray code up/down counter and draw its logic diagram.
10 marks

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OR
11
Using a four bit universal shift register 74194 and design a sequence generator which cycles through the sequence: 0000, 1000, 1100, 0110, 1101, 1011, 0111, 0011, 0001, 000….
10 marks

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