Jawaharlal Nehru Technological University Hyderabad B.Tech II STRUCTURED DIGITAL SYSTEM DESIGN Previous Question Paper (May - 2019 - R13)

Realize 5 input AND function assertion LOW with only two input OR gates.

Draw the Mixed logic equivalent of following expression. Assume A, B are from positive logic system and C, D are from negative logic system.

Draw the symbol and circuit diagram of 2 input open collector output NAND gate.

Define standard load, Fan-in and Fan-out. Write down typical Fan-in and Fan-out values of TTL SN7400 two input NAND gate.

Write down the important specifications of clock oscillators.

Differentiate between Moore and Mealy sequential machines.

Explain Setup time and Hold time.

Draw the truth table and equivalent state diagram for JK flip flop.

Find the number of clock pulses required, to load and to read the data from a 4 bit SISO shift register.

Explain the NAND decoding logic needed for a 4 bit ripple counter to convert it to Mod – 12 counter.

Realize the following Boolean function using 74151 8:1 MUX. F(L) = (ACD' + AB'D + A'B'D' + A'CD + B'C' + AC'D) (L)

Design 4 bit Comparator using Modular Approach using 1 bit Comparator as basic module.

Using 8:1 MUX

Using 4:1 MUX

Explain the term ‘wired logic’. Write the expression for BUS in the given circuit shown in figure 1.

Determine the Pull-up resistor size for a bus wire that has twelve open collector TTL outputs and 16 TTL inputs. Assume VCC = 5 volts, IOUT(1) = 250 µA, IIN(1)=40 µA, IOUT(0) = 15 mA, IIN(0) = -1.6 mA, V0 (1) > = 3 volts and V0(0) < = 0.4 volts.

Discuss in detail, practical aspects related to wired logic and bus oriented structures.

Find the minimum propagation delay of a 4 bit ripple carry adder, if each full adder used requires a 60 ns and 40 ns for producing sum and carry outputs respectively.

Explain the concept of memory and how it yields the invention of binary cell.

Design a clocked JK flip flop using the above binary cell and set/reset decoder.

Design T flip flop using SR flip flop.

Explain how a flip flop is used to divide the input frequency by 2.

Design a synchronous 4 bit counter, which increments by 2 for every clock pulse.

Analyze the following circuit shown in figure 2 and draw corresponding state diagram.

For a synchronous sequential circuit, flip flop equations are given as: JA = C' and KA = C, JB = A' and KB = A, JC = B and KC = B'. Draw the circuit diagram and identify its logic operation.

Find the number of used states and unused states in case of 5 bit ring counter.

Design a Modulo – 6 synchronous binary UP counter using JK flip flops.

Explain the importance of PRESET and CLEAR asynchronous inputs in designing counters.

Design a 4 bit Jhonson counter using suitable shift register and explain its operation.

Design a basic block (jth cell) in case of N-bit universal shift register. Use SR flip flops.