JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II Year STRUCTURED DIGITAL SYSTEM DESIGN Previous Question Paper (April - 2018 - R15)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
Part A
Explain the concept of Inverter.
Answer
An inverter, also known as a NOT gate, is a fundamental logic circuit that performs the logical inversion operation. It takes a single binary input and produces an output that is the logical complement of the input; if the input is logic 0 (low), the output is logic 1 (high), and vice versa.
In digital systems, it is commonly implemented using CMOS technology, where a PMOS transistor is connected to the supply voltage and an NMOS transistor is connected to ground, ensuring that the output is always driven to one of the two stable logic levels.
Draw a 2 bit comparator circuit using 1 bit comparator circuit as basic module.
Answer
A 2-bit comparator compares two 2-bit numbers A (A1A0) and B (B1B0). It can be constructed by cascading two 1-bit comparator modules. The most significant bit (MSB) comparator first checks A1 and B1. If A1 > B1 or A1 < B1, the output is determined immediately. If A1 = B1, the output is determined by the result of the least significant bit (LSB) comparator comparing A0 and B0.
The logic is implemented as follows:
- Let the outputs of the MSB comparator be G1, L1, E1 and the LSB comparator be G0, L0, E0.
- The final outputs (G, L, E) for the 2-bit comparator are:
- G = G1 + (E1 · G0)
- L = L1 + (E1 · L0)
- E = E1 · E0
In this configuration, the equality output E1 of the MSB stage acts as an enable signal for the LSB stage, effectively passing the comparison result to the final output only if the higher-order bits are equal.
Define Noise Margin mention typical values with respect to TTL logic family.
Answer
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List out the advantages of Tri-state logic over binary logic. Draw symbol and truth table of active low Tristate Inverter.
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Explain the basic architectural distinctions between combinational and sequential circuits.
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Draw the diagram of Basic memory cell, expressions for outputs Q(H) and Q(L) in terms of inputs Set(L) and Reset(L). Explain the operation for all possible combinations of inputs.
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Draw the state diagram for 1010 sequence detector.
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Derive excitation table from truth table of JK flip flop.
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Find the maximum clock frequency of a 4 bit ripple counter and 4 bit synchronous counter, if each flip flop has 25ns of propagation delay.
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Explain the NAND decoding logic needed for a 4 bit ripple counter to convert it to Decade counter.
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Part B
Draw logic diagram using AND, OR and INVERTER gates for F = (A'B + C'D + EF') (L) if A, C, E are Asserted HIGH and B,D,F are Asserted LOW inputs.
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Realize the following Boolean function using 74151 8:1 MUX. F(L) = (ABCD' + AB'D + A'B'D' + A'BD + B'C' + C'D) (L)
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Explain Full Adder symbol, truth table and corresponding expressions in Mixed mode logic.
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Explain how an N-bit adder can be implemented with above full adder as a basic block.
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Draw the two input TTL Open collector NAND gate and explain its operation.
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Determine the Pull-up resistor size for a bus wire that has ten open collector TTL outputs and 15 TTL inputs. Assume VCC = 5 volts, IOUT(1) = 250 µA, IIN(1)=40 µA, IOUT(0) = 15 mA, IIN(0) = -1.6 mA, V0 (1) > = 3 volts and V0(0) < = 0.4 volts.
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Explain the operation of Tristate Inverter with Active LOW Enable with neat sketch.
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Find the worst case propagation delay of full adder, if the propagation delay of Ex-OR gate, AND gate and OR gate are 25ns, 20 ns and 15 ns respectively.
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Design a clock oscillator, which generates a 50 Hz frequency.
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Briefly discuss about various oscillator circuits suitable for digital system clocks.
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Design a clocked SR flip flop using binary cell and set/reset decoder.
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Explain Setup time, Hold time and Clock Skew.
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Design a 3 bit synchronous counter using T flip flops with states as: 2 – 4 – 5 – 1 – 7 – 2
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Analyze the flowing circuit and Draw the corresponding state diagram.
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Draw and explain the operation of 4 bit Twisted ring counter using JK flip flops.
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Find the number of used states and unused states in case of 5 bit Twisted ring counter.
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Design a synchronous Modulo – 6 Gray code UP counter.
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Explain the difference between synchronous inputs and asynchronous inputs.
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Draw and explain the operation of 4 bit shift register which can perform both SISO and SIPO operations.
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Find the time required to load and retrieve a 4 bit data from a 4 bit SIPO shift register, if each flip flop has propagation delay of 25 ns.
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