JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II STRUCTURED DIGITAL SYSTEM DESIGN Previous Question Paper (May - 2019 - R15)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks.
Part A
Realize 5 input AND function assertion LOW with only two input OR gates.
Answer
To realize a 5-input AND function with assertion LOW (NAND logic) using only 2-input OR gates, we utilize De Morgan's laws. An AND function with assertion LOW is equivalent to an OR gate with inverted inputs. By applying the identity A AND B = NOT(NOT A OR NOT B), a 5-input AND function can be constructed by inverting all five inputs and feeding them into a tree of 2-input OR gates, then inverting the final output.
The implementation requires inverting the five inputs (A' through E'), connecting them to a cascade of four 2-input OR gates to produce the OR sum, and finally inverting the resulting output to achieve the AND function.
Draw the Mixed logic equivalent of following expression. Assume A, B are from positive logic system and C, D are from negative logic system.
Answer
To represent the expression f = AB + CD using mixed logic, we must convert the negative logic inputs C and D into their positive logic equivalents. In negative logic, a logical 1 is represented by a low voltage (L) and a logical 0 by a high voltage (H). Therefore, the variables C and D are represented by their complements C' and D' in positive logic.
The expression in terms of positive logic variables is:
The mixed logic equivalent circuit consists of two AND gates followed by an OR gate. The inputs A and B are connected directly to the first AND gate. The inputs C and D are passed through inverters (or represented as negative logic pins) before entering the second AND gate, and the outputs of both AND gates are fed into the final OR gate to produce f.
Draw the symbol and circuit diagram of 2 input open collector output NAND gate.
Answer
Sign in to view the complete answer paper.
Define standard load, Fan-in and Fan-out. Write down typical Fan-in and Fan-out values of TTL SN7400 two input NAND gate.
Answer
Sign in to view the complete answer paper.
Write down the important specifications of clock oscillators.
Answer
Sign in to view the complete answer paper.
Differentiate between Moore and Mealy sequential machines.
Answer
Sign in to view the complete answer paper.
Explain Setup time and Hold time.
Answer
Sign in to view the complete answer paper.
Draw the truth table and equivalent state diagram for JK flip flop.
Answer
Sign in to view the complete answer paper.
Find the number of clock pulses required, to load and to read the data from a 4 bit SISO shift register.
Answer
Sign in to view the complete answer paper.
Explain the NAND decoding logic needed for a 4 bit ripple counter to convert it to Mod-12 counter.
Answer
Sign in to view the complete answer paper.
Part B
Realize the Boolean function
Answer
Sign in to view the complete answer paper.
Design 4 bit Comparator using Modular Approach using 1 bit Comparator as basic module.
Answer
Sign in to view the complete answer paper.
Implement the following Boolean function
Using 8:1 MUX
Answer
Sign in to view the complete answer paper.
Using 4:1 MUX. Use extra logic gates if needed.
Answer
Sign in to view the complete answer paper.
Explain the term ‘wired logic’. Write the expression for BUS in the given circuit shown in figure 1.
Answer
Sign in to view the complete answer paper.
Determine the Pull-up resistor size for a bus wire that has twelve open collector TTL outputs and 16 TTL inputs. Assume
Answer
Sign in to view the complete answer paper.
Discuss in detail, practical aspects related to wired logic and bus oriented structures.
Answer
Sign in to view the complete answer paper.
Find the minimum propagation delay of a 4 bit ripple carry adder, if each full adder used requires a 60 ns and 40 ns for producing sum and carry outputs respectively.
Answer
Sign in to view the complete answer paper.
Explain the concept of memory and how it yields the invention of binary cell.
Answer
Sign in to view the complete answer paper.
Design a clocked JK flip flop using the above binary cell and set/reset decoder.
Answer
Sign in to view the complete answer paper.
Design T flip flop using SR flip flop.
Answer
Sign in to view the complete answer paper.
Explain how a flip flop is used to divide the input frequency by 2.
Answer
Sign in to view the complete answer paper.
Design a synchronous 4 bit counter, which increments by 2 for every clock pulse.
Answer
Sign in to view the complete answer paper.
Analyze the following circuit shown in figure 2 and draw corresponding state diagram.
Answer
Sign in to view the complete answer paper.
For a synchronous sequential circuit, flip flop equations are given as:
Answer
Sign in to view the complete answer paper.
Find the number of used states and unused states in case of 5 bit ring counter.
Answer
Sign in to view the complete answer paper.
Design a Modulo – 6 synchronous binary UP counter using JK flip flops.
Answer
Sign in to view the complete answer paper.
Explain the importance of PRESET and CLEAR asynchronous inputs in designing counters.
Answer
Sign in to view the complete answer paper.
Design a 4 bit Jhonson counter using suitable shift register and explain its operation.
Answer
Sign in to view the complete answer paper.
Design a basic block (jth cell) in case of N-bit universal shift register. Use SR flip flops.
Answer
Sign in to view the complete answer paper.