JNTU
JNTU B.Tech II STRUCTURED DIGITAL SYSTEM DESIGN Previous Question Paper (December - 2018 - R15)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
Part A
Show how a full adder can be realized using half adders.
Answer
A full adder is realized using two half adders and an OR gate. The first half adder adds the inputs A and B to produce a sum (S1) and carry (C1). The second half adder adds the sum (S1) and the input carry (Cin) to produce the final sum (S). The final carry (Cout) is obtained by ORing the carry outputs of both half adders (C1 + C2).
Show with an example how a decoder can be used to implement Multiple-input Boolean function.
Answer
A decoder generates all possible minterms for a given number of inputs. To implement a Boolean function, the outputs of the decoder corresponding to the minterms present in the function are connected to an OR gate. For example, to implement F(A,B,C) = Σm(1,3,7) using a 3-to-8 decoder, connect the output pins 1, 3, and 7 of the decoder to a 3-input OR gate.
Define Fan-in and Fan-out.
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Illustrate Propagation delay in a combinational circuit.
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Define race around condition, state how it can be avoided.
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What is sequential circuit? Give examples.
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Give the importance of state reduction.
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Explain the excitation table of JK flip-flop.
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Realize 3-bit ring counter using D flip-flops.
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Draw the logic diagram for 4-bit Serial-In Serial-Out shift register.
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Part B
Explain the functionality of a 4-bit magnitude comparator. Draw its realization diagram.
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Explain the working principle of 3 x 8 Priority encoder with the help of functional table.
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Design a 4-bit parallel adder and explain its functionality with an example.
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Show the realization 12-bit magnitude comparator using 7485 ICs.
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Discuss the practical aspects of Wired Logic in a bus-oriented structures.
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Discuss about tri-state bus system with suitable illustration.
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Explain the wired-AND logic with suitable example.
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Explain the clocking aspect and triggering mechanism in flip flops.
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Using characteristic table and timing diagrams, explain the operation of SR flip-flop.
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Analyze the following clock oscillator shown in figure below using timing diagrams and determine the frequency of oscillation. (Assume the propagation delay through each inverter is 20 nsec)
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Design a clocked SR flip-flop using NAND gates and obtain its characteristic table.
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Discuss the procedure for developing Next state decoder with a suitable design example.
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Discuss the procedure of analyse synchronous sequential circuits.
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Discuss the realization and working principle of 4-bit Johnson counter with timing diagram.
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Design decode counter and then explain its operation with the help of wave forms.
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