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JNTU B.Tech II DIGITAL LOGIC DESIGN Previous Question Paper (April/May - 2023 - R16)

B.Tech | II | II-I | R16 | April/May - 2023

Answer PaperPaper Code: 133AJMaximum Marks: 75Time: 3 Hours

i) Question paper consists of Part A, Part B.

ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions.

iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.

Part A

125 marks

What is meant by self-complementary code? Give examples.

2 marks

Answer

A self-complementary code is a binary code where the 9's complement of a decimal digit is obtained by simply complementing each bit of the code word. Examples include the Excess-3 code and the 8421-2421 code.

Implement the basic gates using only NAND gates.

3 marks

Answer

NOT gate: Connect both inputs of a 2-input NAND gate together.
AND gate: A NAND gate followed by a NOT gate (using a NAND-based inverter).
OR gate: Connect two NAND gates (each acting as an inverter) to the inputs of a third NAND gate.

What are the disadvantages of Karnaugh map?

2 marks

Answer

Simplify the following Boolean function to two literals:

ABC'D + A'BD + ABCD

3 marks

Answer

Implement 2-input NAND gate using 2-to-1 multiplexer.

2 marks

Answer

Draw the 4 to 2 encoder logic diagram.

3 marks

Answer

Differentiate a latch and a flip-flop.

2 marks

Answer

Draw the excitation table for JK flip-flop.

3 marks

Answer

Define RTL and which one is the basic gate in this logic.

2 marks

Answer

Differentiate simple PLDs and Sequential PLDs.

3 marks

Answer

Part B

210 marks

What is the importance of representing a number in compliment form? Explain different signed magnitude representations of binary numbers.

6 marks

Answer

Discuss the properties and applications of XOR gates.

4 marks

Answer

Minimize the following Boolean expression using algebraic manipulation and draw its logic diagram:

f(A, B, C, D) = ABC'D' + ABC'D + AB'C'D + ABCD + AB'CD + ABC'D' + AB'CD'

10 marks

Answer

A warning busser is to sound when the following conditions apply: a) Switches A, B, C are on. b) Switches A and B are on but switch C is off. c) Switches A and C are on but switch B is off. d) Switches B and C are on but switch A is off. Draw a truth table and obtain the simplified Boolean expression using K-map.

10 marks

Answer

Implement a 4-bit even parity checker using 8 to 1 multiplexer.

10 marks

Answer

610 marks

Design a 4-bit magnitude comparator.

5 marks

Answer

Design a 16 × 1 multiplexer using 4 × 1 multiplexers and draw its diagram.

5 marks

Answer

710 marks

Design a code converter that converts a decimal digit from 8,4,-2,-1 code to BCD.

6 marks

Answer

Draw the 4-bit parallel adder circuit diagram.

4 marks

Answer

Design a 3-bit asynchronous binary up counter using T flip-flops.

10 marks

Answer

Show that a Johnson counter with n flip−flops produces a sequence of 2n states. List the 10 states produced with five flip−flops and explain with a neat logic diagram.

10 marks

Answer

Implement 2-bit squarer circuit using programmable array logic.

10 marks

Answer

Explain the arithmetic and logical micro operations with examples.

10 marks

JNTU B.Tech II DIGITAL LOGIC DESIGN Previous Question Paper (April/May - 2023 - R16)

Part A

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Part B

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