Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech II DIGITAL LOGIC DESIGN Previous Question Paper (September/October - 2023 - R16)

B.Tech | II | I | R16 | September/October - 2023

Answer PaperPaper Code: 133AJMaximum Marks: 75Time: 3 Hours

Answer all questions. Part B: Answer any one question from each unit.

Part A

1a

Convert (10110)2 to Gray code and (110101)G to binary number.

2 marks

Answer

To convert the binary number (10110)2 to Gray code, keep the MSB the same and perform XOR operations between adjacent bits:

101102 → 1(1⊕0)(0⊕1)(1⊕1)(1⊕0) = 11101Gray

To convert the Gray code (110101)G to binary, keep the MSB the same and XOR each resulting binary bit with the next Gray code bit:

110101G → 1(1⊕1)(0⊕0)(0⊕1)(1⊕1)(1⊕0) = 1001012
1b

What is Floating point number representation and give examples?

3 marks

Answer

Floating point representation is a method used to represent real numbers that are either very large or very small, allowing for a wide dynamic range. It expresses a number as a product of a mantissa (or significand) and a base raised to an exponent.

N = M × BE

In this format, the mantissa represents the precision of the number, the base is typically 2 for binary systems, and the exponent determines the position of the radix point. This approach is standardized by the IEEE 754 format.

Examples include:

  • Decimal: 123.45 can be represented as 0.12345 × 103, where 0.12345 is the mantissa and 3 is the exponent.
  • Binary: The number 101.1012 is represented as 0.101101 × 23, where the mantissa is 101101 and the exponent is 3.
1c

What are universal gates and why they are called as universal gates?

2 marks

Answer

Sign in to view the complete answer paper.

1d

Draw a four variable Karnaugh map and List its simplification methods.

3 marks

Answer

Sign in to view the complete answer paper.

1e

What is a multiplexer? What is the function of a multiplexer's select input?

2 marks

Answer

Sign in to view the complete answer paper.

1f

Can more than one decoder output be activated at one time? Justify your answer?

3 marks

Answer

Sign in to view the complete answer paper.

1g

What is a flip-flop? Write the logic diagram of J-K flip-flop List all the pins.

2 marks

Answer

Sign in to view the complete answer paper.

1h

Write the difference between synchronous and asynchronous sequential circuits.

3 marks

Answer

Sign in to view the complete answer paper.

1i

What are shift micro operations and what are the different types.

2 marks

Answer

Sign in to view the complete answer paper.

1j

Explain about sequential programmable logic devices.

3 marks

Answer

Sign in to view the complete answer paper.

Part B

210 marks
a

Convert the following: (i) (53.625)10 to ( ? )2 (ii) (3FD)16 to ( ? )2 (iii) (A69.8)16 to ( ? )10

6 marks

Answer

Sign in to view the complete answer paper.

b

Perform the decimal subtraction in 8-4-2-1 BCD using 9's complement (i) Subtract 79 from 26 (ii) Subtract 748 from 983.

4 marks

Answer

Sign in to view the complete answer paper.

OR
310 marks
a

Explain in detail about Weighted, non weighted, Error minimizing and, error detecting and error correcting codes with examples.

6 marks

Answer

Sign in to view the complete answer paper.

b

Check whether the received code 10101100 is correctly received or not if even parity is used.

4 marks

Answer

Sign in to view the complete answer paper.

410 marks
a

Convert the given Boolean function into standard sum of Minterms form. F = x'y+y'z+xz.

4 marks

Answer

Sign in to view the complete answer paper.

b

Simplify the following Boolean function using K-Map method in (i) SOP form (ii) POS form F(A, B, C, D)= Σ(0, 6, 8, 13, 14); Σ d (2, 4,10)

6 marks

Answer

Sign in to view the complete answer paper.

OR
510 marks
a

Reduce using mapping the following expression and implement the real minimal expression in Universal logic. F= Σm (0, 2, 4, 6, 7, 8, 10, 12, 13, 15)

5 marks

Answer

Sign in to view the complete answer paper.

b

Reduce the following expression using k-map f = π M (1, 4, 5, 11, 12, 14) .d (6, 7, 15).

5 marks

Answer

Sign in to view the complete answer paper.

610 marks
a

Explain the full adder and Full Subtractor with the help of a neat logic diagram and truth table.

5 marks

Answer

Sign in to view the complete answer paper.

b

Design a 4:16 decoder with basic gates with control inputs and enable inputs.

5 marks

Answer

Sign in to view the complete answer paper.

OR
710 marks
a

Draw and explain the 8×1 MUX and 3/8 decoder.

5 marks

Answer

Sign in to view the complete answer paper.

b

Explain with neat sketches the working of 4 bit Priority encoder and a 4 bit magnitude comparator.

5 marks

Answer

Sign in to view the complete answer paper.

810 marks
a

What is Race condition and explain about the operation of clocked RS flip flop and D flip-flop.

5 marks

Answer

Sign in to view the complete answer paper.

b

Design a 4 bit shift left register and shift right using D flip-flops.

5 marks

Answer

Sign in to view the complete answer paper.

OR
910 marks
a

Write the differences between synchronous and Asynchronous Counters.

4 marks

Answer

Sign in to view the complete answer paper.

b

Explain the operation of the 4-bit asynchronous counter with a J-K flip-flops and draw its state diagram.

6 marks

Answer

Sign in to view the complete answer paper.

1010 marks
a

Explain the logic implementation of a 32 × 4 bit ROM using decoder of a suitable size.

5 marks

Answer

Sign in to view the complete answer paper.

b

What do you mean by register transfer? Explain in detail. Also discuss three state bus buffer.

5 marks

Answer

Sign in to view the complete answer paper.

OR
1110 marks
a

With a neat diagram explain in detail about two dimensional memory decoding scheme.

4 marks

Answer

Sign in to view the complete answer paper.

b

A combinational circuit is defined by the functions: F1= Σm (3, 5, 7) F2 = Σm( 4,5,7) Implement the circuit with a PLA having 3 inputs, 3 product terms and two outputs.

6 marks

Answer

Sign in to view the complete answer paper.

About this paper

This page contains the question paper of DIGITAL LOGIC DESIGN from Jawaharlal Nehru Technological University Hyderabad for B.Tech IT II I, September/October - 2023, R16.

For the solved question paper with answers, switch to the Answer Paper tab.

Other papers in DIGITAL LOGIC DESIGN

Loading Question Papers

Fetching data from database...