JNTU

JNTU B.Tech II DIGITAL LOGIC DESIGN Previous Question Paper (November/December - 2018 - R16)

B.Tech | II | II-I | R16 | November/December - 2018

Answer PaperPaper Code: 133AJMaximum Marks: 75Time: 3 Hours

Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit.

Part A

1a

Write the advantages of floating-point representation.

2 marks

Answer

The primary advantages of floating-point representation are its ability to represent a significantly wider range of values, including both very large and very small numbers, compared to fixed-point representation. Additionally, it provides a consistent level of precision across this wide range by maintaining a fixed number of significant digits through the normalization of the mantissa.

1b

Distinguish between weighted and non-weighted codes with example.

3 marks

Answer

Weighted codes are those in which each bit position is assigned a specific positional weight, such that the decimal value of a number is calculated by summing the products of each bit and its corresponding weight. An example is the BCD (8421) code, where the weights are 8, 4, 2, and 1.

Non-weighted codes do not assign a fixed positional weight to each bit position. The value represented by the code is not determined by a simple sum of weighted bits, but rather by the specific pattern of the code itself. An example is the Excess-3 code or Gray code, which are used for specific logical properties rather than direct arithmetic weighting.

1c

What is the use of don’t care combinations?

2 marks

Answer

Sign in to view the complete answer paper.

1d

Implement the following function using only NOR Gates F=a.(b+ c) + (b. c).

3 marks

Answer

Sign in to view the complete answer paper.

1e

Define a combinational circuit, give its block diagram.

2 marks

Answer

Sign in to view the complete answer paper.

1f

Write a short notes on priority encoder.

3 marks

Answer

Sign in to view the complete answer paper.

1g

Differentiate between a latch and a flip flop.

2 marks

Answer

Sign in to view the complete answer paper.

1h

Define Hazard. Mention various types of hazards.

3 marks

Answer

Sign in to view the complete answer paper.

1i

Why programmable AND gates are used in PLA instead of a decoder.

2 marks

Answer

Sign in to view the complete answer paper.

1j

Write the applications of logical micro operations.

3 marks

Answer

Sign in to view the complete answer paper.

Part B

210 marks
a

Implement AND, OR, NOR by using NAND gates only.

5 marks

Answer

Sign in to view the complete answer paper.

b

Derive the hamming code for the sequence (101011).

5 marks

Answer

Sign in to view the complete answer paper.

OR
310 marks
a

Convert the following to the corresponding bases: i) (343)5 = ( )6 ii) (7654)8 = ( )10

5 marks

Answer

Sign in to view the complete answer paper.

b

Explain about even and odd parity check with an example, what is the drawback.

5 marks

Answer

Sign in to view the complete answer paper.

410 marks
a

Derive the sum of minterms for f(a,b,c,d)=a'b+ab'd+c'd

5 marks

Answer

Sign in to view the complete answer paper.

b

Derive and Implement Exclusive OR function involving three variables using only NAND function.

5 marks

Answer

Sign in to view the complete answer paper.

OR
510 marks
a

Obtain the simplified expression in POS (product of sums) of F(w,x,y,z)=π(1,2,4,7,12,14,15) using K-maps.

5 marks

Answer

Sign in to view the complete answer paper.

b

Implement the function f(a,b,c)=Σ(1,3,4,6) using NOR-NOR two level gate structure.

5 marks

Answer

Sign in to view the complete answer paper.

6

Realize a full subtractor using decoders.

10 marks

Answer

Sign in to view the complete answer paper.

OR
710 marks
a

Define a multiplexer? Draw a 2:1 multiplexer for the function f(x,y,z)=Σ(0,2,3,5,7)

5 marks

Answer

Sign in to view the complete answer paper.

b

Write the steps involved in designing a combinational circuit.

5 marks

Answer

Sign in to view the complete answer paper.

8

What is the drawback of JK flip flop, design a flip flop which overcomes this drawback and explain with neat diagram.

10 marks

Answer

Sign in to view the complete answer paper.

OR
910 marks
a

Draw the block diagram of asynchronous sequential circuit.

4 marks

Answer

Sign in to view the complete answer paper.

b

Analyze latch with NOR gates, derive transition, flow and state tables.

6 marks

Answer

Sign in to view the complete answer paper.

10

Give the logic implementation of a 32 × 4 bit ROM using decoder of a suitable size.

10 marks

Answer

Sign in to view the complete answer paper.

OR
11

What do you mean by register transfer? Explain in detail. Also discuss Three state bus buffer.

10 marks

Answer

Sign in to view the complete answer paper.

About this paper

This page contains the question paper of DIGITAL LOGIC DESIGN from JNTU for B.Tech IT II II-I, November/December - 2018, R16.

For the solved question paper with answers, switch to the Answer Paper tab.

Other papers in DIGITAL LOGIC DESIGN

Loading Question Papers

Fetching data from database...