JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III DIGITAL SYSTEM DESIGN Previous Question Paper (March - 2024 - R16)
i) Question paper consists of Part A, Part B.
ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions.
iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.
Part A
Define Merger graph.
Answer
A Merger graph is a directed graph used in state reduction of incompletely specified sequential machines. Each state is represented by a node, and an edge is drawn between two nodes if the corresponding states are compatible, indicating they can be merged into a single state.
What is the difference between fundamental mode and pulse mode sequential circuit?
Answer
In fundamental mode circuits, inputs are level-sensitive and must change only when the circuit is stable; it relies on the assumption that only one input changes at a time. In pulse mode circuits, inputs are pulses of specific duration, and the circuit responds to the transition of the pulse, allowing for more complex input timing.
Explain the difference between PLA and PAL with advantages of both.
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Implement 2-bit full adder using ROM.
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What are the rules to be followed when constructing SM block?
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Draw the equivalent SM charts for a combinational circuit Z=A+BC.
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Explain the types of the faults with an example for each.
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Discuss about the single stuck-at faults with example.
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What is a homing tree? Discuss the rules to obtain homing tree.
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Describe the need of functional testing methods.
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Part B
Distinguish about races and hazards.
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Find a circuit that has no static hazards and implements the Boolean function F(A, B, C, D)=Σ(0, 2, 6, 7, 8, 10, 12)
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Describe the procedure for determining the set of equivalent states of a specified machine M with an example.
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Discuss the limitations of the FSM with examples.
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Realize full-adder using 3-8 line decoder and two NOR gates.
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With the help of neat block diagram, explain working of iterative n-bit comparator.
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Design a 3-bit ripple-carry adder using an appropriate PLA with feedback. Specify the PLA size in terms of inputs, total outputs, outputs that feedback to the AND plane of the PLA, and product lines needed for the design.
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Differentiate between the PLA and PAL.
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Draw the SM chat for Dice game and also implement using PLA and D flip flop.
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Discuss in detail the binary multiplier with example. Also obtain the multiplier control with counter.
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Explain the path sensitization method with an example.
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Describe the transition test counting with an example.
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What are the steps in PODEM algorithm and also determine the initial objective and back trace procedure in it.
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Discuss about random testing.
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What is the significance of Fault collapsing? Explain the fault collapsing in EX-OR circuit.
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What is a synchronizing uncertainty vector? And what are the termination rules to obtain synchronizing tree.
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Describe the Transition Check Approach used for Test generation of Sequential Logic Circuits.
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Give the detailed procedure of circuit test approach of sequential circuits.
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