JNTU
JNTU B.Tech III DIGITAL SYSTEM DESIGN Previous Question Paper (November/December - 2020 - R16)
Answer any five questions. All questions carry equal marks.
Main
Explain the procedure for minimization of switching functions using the tabular method with an example.
Answer
The tabular method, also known as the Quine-McCluskey algorithm, is a systematic procedure for simplifying switching functions with a large number of variables where Karnaugh maps become cumbersome. The process consists of two main phases: finding all prime implicants and selecting a minimum set of prime implicants to cover all minterms.
Step 1: Determine Prime Implicants
- List all minterms of the function in binary form, grouped by the number of 1s they contain.
- Compare minterms in adjacent groups. If they differ by exactly one bit position, combine them by replacing that bit with a dash (-). Mark the original minterms as covered.
- Repeat the process for the newly formed terms with dashes, ensuring that dashes align in the same positions. Continue until no further combinations are possible. The remaining unchecked terms are the prime implicants.
Step 2: Prime Implicant Chart
- Construct a table with prime implicants as rows and original minterms as columns.
- Place an 'X' at the intersection of a prime implicant and the minterms it covers.
- Identify essential prime implicants (rows that contain an 'X' in a column where no other row has an 'X').
- Select the essential prime implicants and then choose the minimum number of remaining prime implicants required to cover any uncovered minterms.
Example: Minimize f(A, B, C, D) = Σm(0, 1, 2, 5, 6, 7, 8, 9, 10, 14)
Following the tabular steps, we group by weight: Group 0 (0000), Group 1 (0001, 0010, 1000), Group 2 (0101, 0110, 1001, 1010), Group 3 (0111, 1110). Combining these leads to prime implicants such as 00-0 (A'B'D'), 0-01 (A'C'D), 10-0 (AB'D'), and others. By mapping these to the prime implicant chart, we identify the essential prime implicants that cover all minterms, resulting in the simplified expression: f = A'B'D' + A'C'D + AB'D' + BCD' + A'BC.
What is a Hazard? Explain the design of an SIC Hazard-free circuit.
Answer
A Hazard is an unwanted switching transient that occurs in a combinational circuit when different paths from input to output have different propagation delays. These glitches can cause temporary incorrect output values, which may lead to system errors in sequential circuits.
To design a Static Hazard-Free circuit, one must eliminate the conditions that cause the hazard. A static-1 hazard occurs in an OR-AND implementation when a transition between two input combinations that should produce a constant 1 output momentarily passes through a state where all terms are 0. Similarly, a static-0 hazard occurs in an AND-OR implementation.
The design procedure for a hazard-free circuit involves:
- Obtain the canonical sum-of-products (SOP) expression for the function.
- Map the function onto a Karnaugh map.
- Identify all adjacent 1s that are not covered by the same prime implicant.
- Add redundant prime implicants to the expression such that every pair of adjacent 1s is covered by at least one common product term.
By including these redundant terms, the output remains at a constant logic level during input transitions, effectively masking the delay-induced glitches.
Compare Mealy and Moore models.
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Derive the ROM programming table for the combinational circuit that squares a 4-bit number. Minimize the number of product terms.
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Why are control circuits needed? Explain the operation of a scoreboard controller.
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Develop an ASM chart of a D flip-flop and realize it using only NAND gates.
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Draw the principle components of an SM chart.
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What are the basic elements of an ASM chart? Explain each one clearly with examples.
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For the circuit shown in the figure below:
a) Find the set of all tests that detect the fault a s-a-0
b) Find the set of all tests that detect the fault b s-a-0
c) Find the set of all tests that detect the multiple-fault {a s-a-0, b s-a-0}
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Explain the concept and procedure of Fault detection and location in Sequential circuits.
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