Jawaharlal Nehru Technological University Hyderabad B.Tech II STRUCTURED DIGITAL SYSTEM DESIGN Previous Question Paper (April - 2018 - R13)

Explain the concept of Inverter.

Draw a 2 bit comparator circuit using 1 bit comparator circuit as basic module.

Define Noise Margin mention typical values with respect to TTL logic family.

List out the advantages of Tri-state logic over binary logic. Draw symbol and truth table of active low Tristate Inverter.

Explain the basic architectural distinctions between combinational and sequential circuits.

Draw the diagram of Basic memory cell, expressions for outputs Q(H) and Q(L) in terms of inputs Set(L) and Reset(L). Explain the operation for all possible combinations of inputs.

Draw the state diagram for 1010 sequence detector.

Derive excitation table from truth table of JK flip flop.

Find the maximum clock frequency of a 4 bit ripple counter and 4 bit synchronous counter, if each flip flop has 25ns of propagation delay.

Explain the NAND decoding logic needed for a 4 bit ripple counter to convert it to Decade counter.

Draw logic diagram using AND, OR and INVERTER gates for F = (A'B + C'D + EF') (L) if A, C, E are Asserted HIGH and B,D,F are Asserted LOW inputs.

Realize the following Boolean function using 74151 8:1 MUX. F(L) = (ABCD' + AB'D + A'B'D' + A'BD + B'C' + C'D) (L)

Explain Full Adder symbol, truth table and corresponding expressions in Mixed mode logic.

Explain how an N-bit adder can be implemented with above full adder as a basic block.

Draw the two input TTL Open collector NAND gate and explain its operation.

Determine the Pull-up resistor size for a bus wire that has ten open collector TTL outputs and 15 TTL inputs. Assume VCC = 5 volts, IOUT(1) = 250 µA, IIN(1)=40 µA, IOUT(0) = 15 mA, IIN(0) = -1.6 mA, V0(1) >= 3 volts and V0(0) <= 0.4 volts.

Explain the operation of Tristate Inverter with Active LOW Enable with neat sketch.

Find the worst case propagation delay of full adder, if the propagation delay of Ex-OR gate, AND gate and OR gate are 25ns, 20 ns and 15 ns respectively.

Design a clock oscillator, which generates a 50 Hz frequency.

Briefly discuss about various oscillator circuits suitable for digital system clocks.

Design a clocked SR flip flop using binary cell and set/reset decoder.

Explain Setup time, Hold time and Clock Skew.

Design a 3 bit synchronous counter using T flip flops with states as: 2 – 4 – 5 – 1 – 7 – 2

Analyze the flowing circuit and Draw the corresponding state diagram.

Draw and explain the operation of 4 bit Twisted ring counter using JK flip flops.

Find the number of used states and unused states in case of 5 bit Twisted ring counter.

Design a synchronous Modulo – 6 Gray code UP counter.

Explain the difference between synchronous inputs and asynchronous inputs.

Draw and explain the operation of 4 bit shift register which can perform both SISO and SIPO operations.

Find the time required to load and retrieve a 4 bit data from a 4 bit SIPO shift register, if each flip flop has propagation delay of 25 ns.