JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II STRUCTURED DIGITAL SYSTEM DESIGN Previous Question Paper (December - 2018 - R13)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
Part A
Show how a full adder can be realized using half adders.
Answer
A full adder can be realized using two half adders and one OR gate. The first half adder takes the inputs A and B to produce a sum (S1) and a carry (C1). The second half adder takes the sum S1 and the input carry (Cin) to produce the final sum (S) and a second carry (C2). The final carry output (Cout) is obtained by ORing C1 and C2.
Show with an example how a decoder can be used to implement Multiple-input Boolean function.
Answer
A decoder can implement a Boolean function by using its output lines as minterms. Since a decoder with n inputs generates 2n outputs, each output represents a unique combination of input variables. By connecting the appropriate output lines corresponding to the minterms of the function to an OR gate, the Boolean expression is realized.
For example, to implement the function F(A, B, C) = Σm(1, 3, 7) using a 3-to-8 decoder:
- Connect inputs A, B, and C to the decoder input pins.
- Identify the output lines corresponding to minterms 1, 3, and 7 (labeled Y1, Y3, and Y7).
- Connect these three output lines to the inputs of a 3-input OR gate.
- The output of the OR gate provides the function F = A'B'C + A'BC + ABC.
Define Fan-in and Fan-out.
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Illustrate Propagation delay in a combinational circuit.
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Define race around condition, state how it can be avoided.
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What is sequential circuit? Give examples.
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Give the importance of state reduction.
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Explain the excitation table of JK flip-flop.
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Realize 3-bit ring counter using D flip-flops.
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Draw the logic diagram for 4-bit Serial-In Serial-Out shift register.
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Part B
Explain the functionality of a 4-bit magnitude comparator. Draw its realization diagram.
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Explain the working principle of 3 × 8 Priority encoder with the help of functional table.
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Design a 4-bit parallel adder and explain its functionality with an example.
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Show the realization 12-bit magnitude comparator using 7485 ICs.
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Discuss the practical aspects of Wired Logic in a bus-oriented structures.
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Discuss about tri-state bus system with suitable illustration.
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Explain the wired-AND logic with suitable example.
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Explain the clocking aspect and triggering mechanism in flip flops.
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Using characteristic table and timing diagrams, explain the operation of SR flip-flop.
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Analyze the following clock oscillator shown in figure below using timing diagrams and determine the frequency of oscillation. (Assume the propagation delay through each inverter is 20 nsec)
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Design a clocked SR flip-flop using NAND gates and obtain its characteristic table.
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Discuss the procedure for developing Next state decoder with a suitable design example.
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Discuss the procedure of analyse synchronous sequential circuits.
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Discuss the realization and working principle of 4-bit Johnson counter with timing diagram.
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Design decode counter and then explain its operation with the help of wave forms.
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