JNTU
JNTU B.Tech II STRUCTURED DIGITAL SYSTEM DESIGN Previous Question Paper (March - 2022 - R13)
Answer any five questions. All questions carry equal marks.
Main
Design a module that will check for even or odd parity on two input bits. Extend the design such that it can be cascaded to check the parity over an 8-bit word.
Answer
A parity checker for two bits can be implemented using an XOR gate. If the input bits are A and B, the output Y = A ⊕ B. If Y = 0, the parity is even; if Y = 1, the parity is odd.
To cascade this for an 8-bit word, we use a tree structure of XOR gates. For 8 bits (D7, D6, D5, D4, D3, D2, D1, D0), the parity bit P is calculated as:
This is achieved by connecting the outputs of four 2-bit XOR gates to two subsequent XOR gates, and finally to one last XOR gate. The final output represents the parity of the entire 8-bit word.
Implement the following function using 8:1 MUX. F(A,B,C,D) = ∑m(0,1,3,6,8,13) A and B are ASSERTED LOW, C and D are ASSERTED HIGH.
Answer
To implement F(A,B,C,D) = Σm(0,1,3,6,8,13) using an 8:1 MUX, we use A, B, and C as select lines (S2, S1, S0). The input D is used to determine the data inputs (I0 to I7).
The truth table mapping for the MUX inputs based on D is:
| Select (ABC) | Minterms | MUX Input |
|---|---|---|
| 000 | 0, 1 | D + D' = 1 |
| 001 | 2, 3 | D |
| 010 | 4, 5 | 0 |
| 011 | 6, 7 | D' |
| 100 | 8, 9 | D' |
| 101 | 10, 11 | 0 |
| 110 | 12, 13 | D |
| 111 | 14, 15 | 0 |
Since A and B are asserted low, the select lines are active when the inputs are 0. C and D are asserted high, meaning they are active when the inputs are 1. The MUX data inputs are I0=1, I1=D, I2=0, I3=D', I4=D', I5=0, I6=D, I7=0.
Design a BCD adder circuit.
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Design a 4-bit magnitude comparator circuit using above BCD adder.
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Make a comparison between open collector and tri – state bus system by considering loading, speed etc.
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Determine the PULL – UP Resistor size for a bus wire that has ten open-collector (TTL) outputs and 15 TTL inputs Vcc = 5 volts.
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Define fan-out, fan-in.
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What is the worst case propagation delay of given network shown in figure 1? Δt1 = 10 nSec, Δt2 = 20 nSec, Δt3 = 25 nSec, Δt4 = 10 nSec.
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Design a switch debouncer centered around a 2 input NOR gate.
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Analyze the following clock oscillator as shown in figure 2 using timing diagrams and determine its frequency of oscillation if the propagation delay through each INVERTER = 20 n Sec.
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Differentiate Moore machine from mealy machine.
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Convert an edge triggered D – Flip flop to an edge triggered JK flip flop.
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Design a block diagram and a tight state diagram which monitors an i/p data live [DAT=1(H)] four consecutive times and displays a 3 bit output B2B1B0 after the 4th sample. The o/p is to be the binary equivalent of number of 1 sample in 4 sample sequence.
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Using the state diagram make state assignment for the given state diagram shown in figure 3.
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How a flip-flop is used to divide a frequency.
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Design a modulo-6 Gray code counter. Make your code reflective with respect to the 2nd MSB.
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Write short notes on: i) PROM and its applications. ii) FPLA’s architecture.
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